1、实现思路其实就是矩阵的乘法,对应的simulink模块如下:
2、实验代码:需要的请联系作者邮箱!
实验测试代码:
`timescale 1ns / 1ps
//
// Company: 东北电力大学
// Engineer: Yang Zheng
//
// Create Date: 2022/07/02 11:51:05
// Design Name:
// Module Name: testbench
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//
module testbench(
);
// Filter_lowpass Parameters
parameter PERIOD = 10;
// Filter_lowpass Inputs
reg clk = 0 ;
reg rst = 0 ;
reg [2 * 2 * 32 -1 : 0] x_in = 0 ;
reg [31 : 0] u_in = 0 ;
reg Filter_lowpass_input_valid = 0 ;
// Filter_lowpass Outputs
wire [2 * 2 * 32 -1 : 0] x_out ;
wire [2 * 32 - 1 : 0] u_out ;
wire Filter_lowpass_output_valid ;
wire Filter_lowpass_valid_en ;
initial
begin
forever #(PERIOD/2) clk=~clk;
end
initial
begin
#(PERIOD*2) rst = 1;
end
reg [31:0] test [2:0][1:0][1:0];
Filter_lowpass u_Filter_lowpass (
.clk ( clk ),
.rst ( rst ),
.x_in ( x_in [2 * 2 * 32 -1 : 0] ),
.u_in ( u_in [31 : 0] ),
.Filter_lowpass_input_valid ( Filter_lowpass_input_valid ),
.x_out ( x_out [2 * 2 * 32 -1 : 0] ),
.u_out ( u_out [2 * 32 - 1 : 0] ),
.Filter_lowpass_output_valid ( Filter_lowpass_output_valid ),
.Filter_lowpass_valid_en ( Filter_lowpass_valid_en )
);
always @(posedge clk or negedge rst) begin
if (!rst) begin
end
else begin
{test[0][0][0],test[0][0][1],test[0][1][0],test[0][1][1]}<=32'h3F800000;
{test[1][0][0],test[1][0][1],test[1][1][0],test[1][1][1]}<=32'h40000000;
{test[2][0][0],test[2][0][1],test[2][1][0],test[2][1][1]}<=32'h40400000;
if (Filter_lowpass_valid_en) begin
Filter_lowpass_input_valid <= 1'b1;
x_in <= {32'h3F800000,32'h40000000,32'h40400000,32'h40800000};
u_in <= 32'h3DF89613;
end
end
end
endmodule
测试结果如下: