HDLBits
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HDLBits Design a Moore FSM Examsece241 2013 q4
HDLBits Design a Moore FSM Exams/ece241 2013 q4网址:https://hdlbits.01xz.net/wiki/Exams/ece241_2013_q4题目大意是设计一个记录水位的状态机,可以设计六个状态表示表格中的water level,其中Between s3 and s2与between s2 and s3分别用两个表示上升至该水位或下降至该水位,Above S3和Below S1用两个状态表示。module top_module ( in原创 2022-04-05 21:10:14 · 342 阅读 · 0 评论 -
HDLBits PS2
HDLBits PS/2Fsm ps2网址:https://hdlbits.01xz.net/wiki/Fsm_ps2The PS/2 mouse protocol sends messages that are three bytes long. However, within a continuous byte stream, it’s not obvious where messages start and end. The only indication is that the first b原创 2022-03-23 16:19:04 · 229 阅读 · 0 评论 -
HDLBits Lemmings1-4
HDLBits Lemmings1-4Lemming1网址:https://hdlbits.01xz.net/wiki/Lemmings1The game Lemmings involves critters with fairly simple brains. So simple that we are going to model it using a finite state machine.In the Lemmings’ 2D world, Lemmings can be in one o原创 2022-03-22 22:02:34 · 363 阅读 · 0 评论 -
HDLbits Count clock
HDLbits Count clockCreate a set of counters suitable for use as a 12-hour clock (with am/pm indicator). Your counters are clocked by a fast-running clk, with a pulse on ena whenever your clock should increment (i.e., once per second).reset resets the clo原创 2022-03-17 16:32:49 · 543 阅读 · 0 评论 -
HDLBits Countbcd
HDLBits Countbcd网址:https://hdlbits.01xz.net/wiki/CountbcdBuild a 4-digit BCD (binary-coded decimal) counter. Each decimal digit is encoded using 4 bits: q[3:0] is the ones digit, q[7:4] is the tens digit, etc. For digits [3:1], also output an enable sign原创 2022-03-16 19:29:39 · 185 阅读 · 0 评论 -
HDLBits Edgecapture
Edgecapture网址:https://hdlbits.01xz.net/wiki/EdgecaptureFor each bit in a 32-bit vector, capture when the input signal changes from 1 in one clock cycle to 0 the next. “Capture” means that the output will remain 1 until the register is reset (synchronous原创 2022-03-15 11:31:06 · 423 阅读 · 0 评论 -
HDLBits Examsece241 2014 q5a
HDLBits Exams/ece241 2014 q5a1.题目 题目链接:https://hdlbits.01xz.net/wiki/Exams/ece241_2014_q5a You are to design a one-input one-output serial 2’s complementer Moore state machine. The input (x) is a series of bits (one per clock cycle) beginning with the原创 2021-12-01 21:29:04 · 1080 阅读 · 0 评论 -
HDLBits FSMHDLC
HDLBits FSMHDLC1.题目 {#1题目}Synchronous HDLC framing involves decoding a continuous bit stream of data to look for bit patterns that indicate the beginning and end of frames (packets). Seeing exactly 6 consecutive 1s (i.e., 01111110) is a “flag” that indic原创 2021-12-01 18:33:08 · 331 阅读 · 0 评论