HDLBits Edgecapture

HDLBits Edgecapture

网址：https://hdlbits.01xz.net/wiki/Edgecapture

For each bit in a 32-bit vector, capture when the input signal changes from 1 in one clock cycle to 0 the next. “Capture” means that the output will remain 1 until the register is reset (synchronous reset).

Each output bit behaves like a SR flip-flop: The output bit should be set (to 1) the cycle after a 1 to 0 transition occurs. The output bit should be reset (to 0) at the positive clock edge when reset is high. If both of the above events occur at the same time, reset has precedence. In the last 4 cycles of the example waveform below, the ‘reset’ event occurs one cycle earlier than the ‘set’ event, so there is no conflict here.

In the example waveform below, reset, in[1] and out[1] are shown again separately for clarity.

题目意思就是捕捉in的下降沿，只有在in从1->0变化时out会输出1，其他情况out不会改变。

in_p为in的前一个时钟周期状态，可用D触发器实现。

对应的状态关系为：

in_p	in	out
0	0	out
0	1	out
1	0	1
1	1	out

由上表可得out与in_p和in的表达式：out[i]<=(in_p[i]&in[i])?1:out[i];

module top_module(
	input clk,
    input reset,
    input [31:0] in,
    output [31:0] out
);
    wire [31:0] in_p;
    int i;
    always @(posedge clk) begin
    	in_p<=in;
    end
    always @(posedge clk) begin
        if(reset) out<=32'b0;
        else 
            for(i=0;i<32;i=i+1) 
                out[i]<=(in_p[i]&~in[i])?1:out[i];
        
    end
endmodule