verilog语言练习2

`timescale 1ns/1ns

module  lowhight_tb;

  reg Clk;
  reg Rst_n;
  reg en;
  reg [7:0] data;
  
  
  wire tx;
  wire tx_done; //根据完成信号控制en

  lowhight  lowhight(
     .Clk(Clk),
	  .Rst_n(Rst_n),
	  .en(en),
	  .data(data),
	  .tx_done(tx_done),
     .tx(tx)
	  
);

initial Clk=1;
always #10 Clk =  ~Clk;


initial begin
  Rst_n = 0;  
  data=0;
  en=0;
  #200;
  Rst_n=1;   
  #200;
  
  en=1;
  data=8'h12;
  @(posedge tx_done); //等tx_done来为止才进行下面操作
  en=0;//en为0
  #50000;
  
  
  en=1;
  data=8'h56;
  @(posedge tx_done); //等tx_done来为止才进行下面操作
  en=0;//en为0
  #50000;
  
  
  en=1;
  data=8'haf;
  @(posedge tx_done); //等tx_done来为止才进行下面操作
  en=0;//en为0
  #50000;
  
  $stop;
end

endmodule

`timescale 1ns/1ns

module  lowhight_tb;

  reg Clk;
  reg Rst_n;
  reg en;
  reg [7:0] data;
  
  
  wire tx;
  wire tx_done; //根据完成信号控制en

  lowhight  lowhight(
     .Clk(Clk),
	  .Rst_n(Rst_n),
	  .en(en),
	  .data(data),
	  .tx_done(tx_done),
     .tx(tx)
	  
);

initial Clk=1;
always #10 Clk =  ~Clk;


initial begin
  Rst_n = 0;  
  data=0;
  en=0;
  #200;
  Rst_n=1;   
  #200;
  
  en=1;
  data=8'h12;
  @(posedge tx_done); //等tx_done来为止才进行下面操作
  en=0;//en为0
  #50000;
  
  
  en=1;
  data=8'h56;
  @(posedge tx_done); //等tx_done来为止才进行下面操作
  en=0;//en为0
  #50000;
  
  
  en=1;
  data=8'haf;
  @(posedge tx_done); //等tx_done来为止才进行下面操作
  en=0;//en为0
  #50000;
  
  $stop;
end

endmodule