题目
设计电路,完成以下功能:每瓶饮料1.5元,一次只能投入一个硬币,可投入0.5与1.0两种硬币,具有找零功能。
分析:由于一次只能投入一个硬币,且具有找零的功能,因此,饮料机内的余额必定小于1.5,通过分析,不难得到余额只可能是0,0.5,1.0这三种情况,因此,我们可以设置4个状态:
IDLE:复位状态
S1:余额为0
S2:余额为0.5
S3:余额外为1
我们以2bit信号为输入,若高位为1,表示投入1元,否则表示投入0.5元,若都为0,则表示不投入钱,不存在同时为1的情况(一次只能投入一个硬币)。输出drink信号为1位,当它为1时表示输出饮料,则有如下状态机
代码实现
`timescale 1ns / 1ps
//
// Company:
// Engineer:
//
// Create Date: 2022/03/03 13:45:48
// Design Name:
// Module Name: drink_machine
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//
module drink_machine(
input logic clk,
input logic rst,
input logic [1:0] money,
output logic drink,
output logic money_back //找零0.5或0
);
typedef enum bit [1:0] {
IDLE,
S1, //余额为0
S2, //余额为0.5
S3 //余额为1.0
} STATE;
STATE cur_state,next_state;
//
always_ff@(posedge clk,posedge rst)
if(rst)
cur_state<=IDLE;
else
cur_state<=next_state;
//
always_comb
begin
case(cur_state)
IDLE:if(rst)
begin
next_state=IDLE;
drink=0;
money_back=0;
end
else if(money==2'b00)
begin
next_state=S1;
drink=0;
money_back=0;
end
else if(money==2'b01)
begin
next_state=S2;
drink=0;
money_back=0;
end
else
begin
next_state=S3;
drink=0;
money_back=0;
end
S1:if(money==2'b00) //余额为0
begin
next_state=S1;
drink=0;
money_back=0;
end
else if(money==2'b01) //0.5
begin
next_state=S2;
drink=0;
money_back=0;
end
else //money=10,1元
begin
next_state=S3;
drink=0;
money_back=0;
end
S2:if(money==2'b00) //余额为0.5
begin
next_state=S2;
drink=0;
money_back=0;
end
else if(money==2'b01) //0.5+0.5%1.5=1
begin
next_state=S3;
drink=0;
money_back=0;
end
else //0.5+1%1.5=0
begin
next_state=IDLE;
drink=1;
money_back=0;
end
S3:if(money==2'b00)
begin
next_state=S3;
drink=0;
money_back=0;
end
else if(money==2'b01)
begin
next_state=IDLE;
drink=1;
money_back=0;
end
else
begin
next_state=IDLE;
drink=1;
money_back=1; //找0.5
end
default:begin
next_state=IDLE;
drink=0;
money_back=0;
end
endcase
end
endmodule
测试平台
`timescale 1ns / 1ps
//
// Company:
// Engineer:
//
// Create Date: 2022/03/03 14:12:56
// Design Name:
// Module Name: sim_tb
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//
module sim_tb;
logic clk;
logic rst;
logic [1:0] money;
logic drink;
logic money_back;
//clk
initial begin
clk=0;
forever begin
#5 clk=~clk;
end
end
//rst
initial
begin
rst=1;
#100
rst=0;
end
//money
initial
begin
money=2'b00;
repeat(10)
@(posedge clk);
money=2'b01;
@(posedge clk);
money=2'b00;
repeat(2)
@(posedge clk);
money=2'b10; //完成购买
@(posedge clk);
money=2'b00;
repeat(10)
@(posedge clk);
money=2'b10;
@(posedge clk);
money=2'b00;
repeat(3)
@(posedge clk);
money=2'b10; //第二次购买完成
@(posedge clk);
money=2'b00;
repeat(10)
@(posedge clk);
money=2'b01;
repeat(2)
@(posedge clk); //连续投入2个0.5
money=2'b00;
repeat(2)
@(posedge clk);
money=2'b01; //投入0.5
@(posedge clk);
money=2'b00;
repeat(4)
@(posedge clk);
money=2'b01; //投入两个0.5
repeat(2)
@(posedge clk);
money=2'b00;
repeat(5)
@(posedge clk);
money=2'b10; //投入一个1.0
@(posedge clk);
money=2'b00;
end
drink_machine U(.*);
// input logic clk,
// input logic rst,
// input logic [1:0] money,
// output logic drink,
// output logic money_back //找零0.5或0
// );
endmodule
仿真结果
波形图如下,已在图中进行了分析。