HDLBits-Vector reversal 1

Given an 8-bit input vector [7:0], reverse its bits ordering.

module top_module(
    input [7:0] in,
    output [7:0] out
    );

    assign out = {in[0], in[1], in[2], in[3], in[4], in[5], in[6], in[7]};

endmodule

for-loops:

integer i;
always @ (*) begin
    for(i = 0; i < 8; i = i + 1)
        out[i] = in[7-i];
end

generate-for:

generate
    genvar i;
    for(i = 0; i < 8; i = i + 1) begin: my_block_name
        assign out[i] = in[7-i];
    end        
endgenerate