HDLBits-Lemmings4

题目：

状态机：

 

 代码：

module top_module(
    input clk,
    input areset,    // Freshly brainwashed Lemmings walk left.
    input bump_left,
    input bump_right,
    input ground,
    input dig,
    output walk_left,
    output walk_right,
    output aaah,
    output digging ); 
    
    parameter S0 = 7'b0000001;
    parameter S1 = 7'b0000010;
    parameter S2 = 7'b0000100;
    parameter S3 = 7'b0001000;
    parameter S4 = 7'b0010000;
    parameter S5 = 7'b0100000;
    parameter S6 = 7'b1000000;
    
    reg [6:0] state;
    reg [15:0] cnt;
    reg [3:0] out;
    
    assign {walk_left,walk_right,aaah,digging} = out;
    
    always @ (posedge clk or posedge areset) begin
        if(areset)
            cnt <= 15'd0;
        else if(~ground)
            cnt <= cnt + 15'd1;
        else if(ground)
            cnt <= 15'd0;
        else
            cnt <= cnt;
    end
    
    always @ (posedge clk or posedge areset) begin
        if(areset)
            state <= S0;
        else begin
            case(state)
                S0:begin
                	if(~ground)
                        state = S2;
                    else if(dig)
                        state = S3;
                    else if(bump_left)
                        state = S1;
                    else
                        state = S0;   	 
                end
                S1:begin
                    if(~ground)
                        state = S4;
                    else if(dig)
                        state = S5;
                    else if(bump_right)
                        state = S0;
                    else
                        state = S1;
                end
                S2:begin
                    if(cnt >= 5'd21 && ground)
                        state = S6;
                    else if(cnt < 5'd21 && ground)
                        state = S0;
                    else
                        state = S2;
                end
                S3:begin
                    if(~ground)
                        state = S2;
                    else
                        state = S3;
                end
                S4:begin
                    if(cnt >= 5'd21 && ground)
                        state = S6;
                    else if(cnt < 5'd21 && ground)
                        state = S1;
                    else
                        state = S4;
                end
                S5:begin
                    if(~ground)
                        state = S4;
                    else
                        state = S5;
                end
                S6:begin
                    state = S6; 
                end
                default:state = S0;
            endcase
        end
    end
    
    always @ (*) begin
        case(state)
            S0:begin
                out = 4'b1000;
            end
            S1:begin
                out = 4'b0100;
            end
            S2:begin
                out = 4'b0010;                
            end
            S3:begin
                out = 4'b0001;
            end
            S4:begin
                out = 4'b0010;
            end
            S5:begin
                out = 4'b0001;
            end
            S6:begin
                out = 4'b0000;
            end
            default:begin
                out = 4'b1000;
            end
        endcase
    end

endmodule

注意：

状态机可以写成一段式、二段式和三段式，实际可以根据自己的需求来，最终目标是要保证时序正确。