FPGA作业一--全加器

串行全加器

module full_adder(a,b,Cin,sum,Cout);

    input a,b;
    input Cin;

    output sum;
    output Cout;

    wire t1,t2,t3;
    wire s1;

    xor (s1,a,b);
    xor (sum,s1,Cin);
    and (t3,a,b);
    and (t2,b,Cin);
    and (t1,a,Cin);
    or (Cout,t1,t2,t3);

endmodule

module test(a,b,Cin,sum,Cout);
    input [2:0] a,b;
    input Cin;
    output [2:0]sum;
    output Cout;
    wire Cout1,Cout2;

    full_adder f1(a[0],b[0],Cin,sum[0],Cout1);
    full_adder f2(a[1],b[1],Cout1,sum[1],Cout2);
    full_adder f3(a[2],b[2],Cout2,sum[2],Cout);


endmodule

测试代码

//参考时间单位为100ns，精度为1ns
`timescale 100ns /1ns  
 
module test_tb;
 
	// Inputs 声明输入信号  用寄存器变量reg型
	reg [2:0] a;
	reg [2:0] b;
 	reg Cin;
	// Outputs 声明输出信号  用线性wire型
	wire [2:0] sum;
	wire cf;

 
	// Instantiate the Unit Under Test (UUT)   调用待测试模块
	test uut (
		.a(a), 
		.b(b), 
		.Cin(Cin),
		.sum(sum), 
		.Cout(cf)
	);
 
	initial begin
		// Initialize Inputs  初始化
		a = 0;
		b = 0;
		Cin=0;
		// Wait 100 ns for global reset to finish
//给输入变量一个值，等待100ns，从仿真程序中可以看到输出的结果
		#100;
		a = 3'b100;
		b = 3'b001;
	   #100;
		a = 3'b100;
		b = 3'b011;
       #100;
		a = 3'b100;
		b = 3'b010;
       #100;
		a = 3'b101;
		b = 3'b001;
       #100;
		a = 3'b111;
		b = 3'b101;
        
		// Add stimulus here
 
	end
//显示输出与输入
	/*
	initial 
	$monitor($time,
	":\a-%b,b=%b,sum=%b,cf=%b\n",a,b,sum,cf);
    */
endmodule