HDLBits_12 hour clock_使用模块例化

使用六进制、十进制、十二进制三个模块例化（貌似能简化成两个模块？）

module top_module(
    input clk,
    input reset,
    input ena,
    output pm,
    output [7:0] hh,
    output [7:0] mm,
    output [7:0] ss); 
	
    wire ena_s,ena_m1,ena_m2,ena_h;  //进位计数信号
	
    assign ena_s = (ss[3:0] == 4'd9 && ena == 1);
    assign ena_m1 = (ss == 8'h59 && ena == 1);
    assign ena_m2 = (mm[3:0] == 4'd9 && ena == 1 && ss == 8'h59);
    assign ena_h = (mm == 8'h59 && ena == 1 && ss == 8'h59);
	
    count10 s1(clk, reset, ena, ss[3:0]);
    count6 s2(clk, reset, ena_s, ss[7:4]);
    count10 m1(clk, reset, ena_m1, mm[3:0]);
    count6 m2(clk, reset, ena_m2, mm[7:4]);
    counth h(clk, reset, ena_h, hh[7:0], pm);
  
endmodule
module count10(input clk, input reset, input ena, output reg[3:0] out);
    always@(posedge clk)
        if(reset)
            out <= 0;
    else if(ena)begin
        if(out >= 4'd9)
            out <= 0;
        else
            out <= out + 1;
    end
    else out <= out;
endmodule

module count6(input clk, input reset, input ena, output reg[3:0] out);
    always@(posedge clk)
        if (reset)
            out <= 0;
    else if(ena)begin
        if(out >= 4'd5)
            out <= 0;
        else
            out <= out + 1;
    end
    else out <= out;
endmodule

module counth(input clk, input reset, input ena, output reg[7:0] out, output reg pm);
    always@(posedge clk)
        if(reset)begin
            out <= 8'h12;
            pm <= 0;
        end
    else if(ena)begin
        if(out >= 8'h12)
            out <= 8'h01; 
        else if(out == 8'h11)begin
            pm <= ~pm;
            out <= out + 1;
        end
        else if(out == 8'h09)
            out <= 8'h10;
        else
            out <= out + 1;
    end
    else out <= out;
endmodule