HDLBits_countbcd(多位bcd十进制计数器普适)

只需将一个4位bcd计数器模块多次例化，然后采用生成块语法可精简代码

并且普适n*4位bcd十进制计数器

module top_module (
    input clk,
    input reset,   // Synchronous active-high reset
    output [3:1] ena,
    output [15:0] q);

    bcd bcd1(clk, reset, 1, q[3:0]);
	
	genvar i;
	generate
        for(i=1;i<4;i++)begin:ins
	bcd bcd_n(clk, reset, ena[i], q[4*i+3:4*i]);
            assign ena[i] = (q[4*i-1:0] == {i{4'd9}});
        end
    endgenerate
endmodule

module bcd(input clk, input reset, input ena, output reg [3:0]q);
    always@(posedge clk)
        if(reset)
            q <= 0;
    else if(ena)begin
        if(q >= 4'd9)
            q <= 0;
        else
        q <= q + 1;
    end
    else q <= q;
endmodule