沿用上一题独热码思想
module top_module(
input clk,
input in,
input areset,
output out); //
parameter A=0,B=1,C=2,D=3;
wire [3:0]state, next;
assign next[A] = (state[A]&~in) | (state[C] & ~in);
assign next[B] = (state[A]&in) | (state[D]&in) | (state[B]&in);
assign next[C] = (state[B]&~in) | (state[D]&~in);
assign next[D] = (state[C]&in);
// State transition logic
always@(posedge clk or posedge areset)
if(areset)
state <= 1;
else state <= next;
// State flip-flops with asynchronous reset
assign out = (state[D] == 1);
// Output logic
endmodule