源码:module AJXD(
input clk,
input rst_n,
input key,
output reg key_out
);
wire out_pos;
wire out_neg;
reg key_s1;
reg key_cnt;
always@(posedge clk)
begin
if(~rst_n)
key_s1<=1;
else
key_s1<=key;
end
assign out_pos=key&~key_s1;
assign out_neg=~key&key_s1;
reg [3:0]cnt;
always@(posedge clk)
begin
if(~rst_n)
cnt<=0;
else if(key_cnt)
cnt<=0;
else
cnt<=cnt+1’b1;
end
always@(posedge clk)
begin
if(~rst_n)
key_cnt<=0;
else if(out_pos1||out_neg1)
key_cnt<=1;
else
key_cnt<=0;
end
always@(posedge clk or negedge rst_n)
begin
if(~rst_n)
key_out<=1;
else if(cnt==2)
key_out<=key;
end
endmodule
激励
`timescale 1ns/1ns
module AJXD_tb();
reg clk;
reg rst_n;
reg key;
initial
begin
rst_n=0;
#300 rst_n=1;
#10000 $stop;
end
initial
begin
clk=0;
end
initial
begin
key=1;
#200 key=1;
#200 key=1;
#10 key=0;
#10 key=1;
#10 key=0;
#10 key=1;
#10 key=0;
#10 key=1;
#10 key=0;
#200 key=0;
#200 key=0;
#10 key=0;
#10 key=1;
#10 key=0;
#10 key=1;
#10 key=0;
#10 key=1;
#200 key=1;
#200 key=1;
#200 key=1;
end
always #10 clk<=~clk;
AJXD AJXD_out(
.clk(clk),
.rst_n(rst_n),
.key(key),
.key_out()
);
endmodule
原理:(在激励中定义信号模拟按键产生的毛刺)
根据沿检测的原理,只要检测到有沿产生,用一个计数器把它加一,当如果有沿的时候就置为零。然后在计数器等于一个常数时,说明信号稳定,然后输出。