VSLAM 硬件（FPGA、ASIC）架构设计论文汇总（一直更新）

最新推荐文章于 2023-10-25 18:38:58 发布

Ocean_VV

最新推荐文章于 2023-10-25 18:38:58 发布

阅读量1.1k

点赞数 2

分类专栏： vision slam FPGA、Verilog 文章标签： VSLAM 硬件设计

本文链接：https://blog.csdn.net/qq_41634276/article/details/119718884

版权

FPGA、Verilog 同时被 2 个专栏收录

17 篇文章 10 订阅

订阅专栏

vision slam

5 篇文章 4 订阅

订阅专栏

为了便于大家可以快速查阅与VSLAM（Visual SLAM）硬件架构设计相关的最新论文，特整理到此博客中，会一直更新，包含JSSC期刊、ISSCC、VLSI、ISCA、HPCA、MICRO、DAC、FPGA、FCCM、FPL、PFT等会议

2021：

JSSC：

A 1.5- J/Task Path-Planning Processor for 2-D/3-D Autonomous Navigation of Microrobots（Chieh Chung，NTU）
NeuroSLAM: A 65-nm 7.25-to-8.79-TOPS/W Mixed-Signal Oscillator-Based SLAM Accelerator for Edge Robotics（Arijit Raychowdhury，Georgia Institute of Technology）

ISSCC：

A 12nm Autonomous-Driving Processor with 60.4TOPS, 13.8TOPS/W CNN Executed by Task-Separated ASIL D Control（Katsushige Matsubara ，Renesas Electronics）

HPCA：

Eudoxus: Characterizing and Accelerating Localization in Autonomous Machines（Shaoshan Liu，Yiming Gan，Perceptln）

2020：

JSSC：

A 20.5 TOPS Multicore SoC With DNN Accelerator and Image Signal Processor for Automotive Applications（Yutaka Yamada，东芝电子）

ISSCC:

A 1.5μJ Task Path-Planning Processor for 2D 3D Autonomous Navigation of Micro Robots(Chieh Chung，NTU）
A 65nm 8.79TOPS/W 23.82mW Mixed-Signal Oscillator- Based NeuroSLAM Accelerator for Applications in Edge Robotics (Arijit Raychowdhury，Georgia Institute of Technology）

VLSI:

A 1200x x1200 8-Edges/Vertex FPGA-based Motion-Planning Accelerator for Dual-Arm-Robot Manipulation System (Takashi Oshima, Renesas Electronics)

DAC:

INCA: INterruptible CNN Accelerator for Multi-tasking in Embedded Robots( Jincheng Yu, THU)
PISCES: Power-Aware Implementation of SLAM by Customizing Effificient Sparse Algebra( Bahar Asgari, Georgia Institute of Technology)

FCCM:

An FPGA-Optimized Architecture of Real-time Farneback Optical Flow( Zhe Pan, 浙大）
CNN-based Feature-point Extraction for Real-time Visual SLAM on Embedded FPG（ Yu Wang，THU）

2019：

JSSC：

A 55-nm, 1.0 0.4V, 1.25-pJ/MAC Time-Domain Mixed-Signal Neuromorphic Accelerator With Stochastic Synapses for Reinforcement Learning in Autonomous Mobile Robots ( Arijit Raychowdhury，Georgia Institute of Technology）
A 1920x1080 25-Frames/s 2.4-TOPS/W Low-Power 6-D Vision Processor for Unified Optical Flow and Stereo Depth With Semi-Global Matching( David Blaauw, Ziyun Li, Michigan )
Navion: A 2mW Fully Integrated Real-Time Visual-Inertial Odometry Accelerator for Autonomous Navigation of Nano Drones( Vivienne Sze, MIT )

ISSCC:

An 879GOPS 243mW 80fps VGA Fully Visual CNN-SLAM Processor for Wide-Range Autonomous Exploration( David Blaauw, Ziyun Li, Michigan )

MICRO:

ASV: Accelerated Stereo Vision System( Yu Feng, Rochester)

DAC:

eSLAM: An Energy-Efficient Accelerator for Real-Time ORB-SLAM on FPGA Platform( Weisheng Zhao, Yiran Chan, 北航，Duke）

FPGA：

A FPGA Implementation of Farneback Optical Flow by High-Level Synthesis（ Chiawei Chang，NTHU）

FCCM：

A 4.8x Faster FPGA-Based Iterative Closest Point Accelerator for Object Pose Estimation of Picking Robot Applications（ Atsutake Kosuge，日立）

2018：

VLSI：

Navion: A Fully Integrated Energy-Efficient Visual-Inertial Odometry Accelerator for Autonomous Navigation of Nano Drones( Vivienne Sze, MIT )
A 1920x1080 25fps, 2.4TOPS/W Unified Optical Flow and Depth 6D Vision Processor for Energy-Efficient, Low Power Autonomous Navigation( David Blaauw, Ziyun Li, Michigan )