# 自动售饮料机逻辑电路的设计

1，逻辑抽象：

2，状态转化图：

3，用Verilog语言描述电路设计

//售货机模块

module VendingMachine(

input A, B, clk, reset,

output wire Y, Z);

//描述时用到的时间变量

reg [1:0] state;

wire    [1:0] in;

reg    [1:0] out;

assign Y=out[1];

assign Y=out[0];

//根据设计，对输入变量的取值，以及状态进行编码

parameter S0=2’b00, S1=2’b01, S2=2’b10;

parameter NONE=2’b00, GOODS=2’b10, S2=2’b11;

parameter COIN_00=2’b00, COIN_05=2’b01, COIN_10=2’b10;

//同步状态转换模块

always@(posedge clk or postdge reset) begin

if (reset)

state <=S0;

else if (state==S0)

begin

if (in==COIN_00)                   state<=S0;

else if(in==COIN_05)             state<=S1;

else if(in==COIN_10)             state<=S2;

else                                      state<=S0;

end

else if (state==S1)

begin

if (in==COIN_00)                   state<=S1;

else if (in==COIN_05)            state<=S2;

else if (in==COIN_10)            state<=S0;

else                                        state<=S0;

end

else if (state==S2)

begin

if (in==COIN_00)                   state<=S2;

else if (in==COIN_05)            state<=S0;

else if (in==COIN_10)            state<=S0;

else                                       state<=S0;

end

end

//输出模块，此例为Mealy型设计

always@ (state or in)

begin

if (state==S0)          out=NONE;

else if (state==S1)

begin

if (in==COIN_0 || in==COIN_05)    out=NONE;

else if (in==COIN_10)              out=GOODS;

else

end

else if (state==S2)

begin

if (in==COIN_00)                             out=NONE;

else if (in==COIN_05)             out=GOODS;

else if (in==COIN_10)             out=ALL;

else                              out=NONE;

end

end

endmodule

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