FPGA的一些整理

1.阻塞赋值与非阻塞赋值

阻塞赋值可以理解为语句的顺序执行，因此语句的执行顺序很重要。非阻塞赋值可以理解为语句的并行执行，所以语句的执行不考虑顺序。在assign的结构中，必须使用的是阻塞赋值。

always@(posedge clk)
    begin
        b <= a;
        c <= b;
    end 

这样a传递到c需要1个时钟

2.同步信号与异步信号

异步信号和时钟信号无关，而同步信号和时钟信号有关。例如异步复位只要复位信号有效即可清零，同步清零要求复位信号有效并且时钟为上升沿或下降沿时才能清零。

3.verilog产生随机数的三种情况

reg a,b,c;
a <= {$random}; //无符号随机数
b <= $random%100; //产生一个在-99-99范围的随机数
c <= {$random}%100; //产生一个0—99范围的随机数

4. 2的倍次的乘除用移位操作代替，节省资源

5.task与function的用法

module task_test(
input   wire        clk,
input   wire        rst,
input   wire        start,
input   wire[7:0]   data_in,
output  reg [7:0]   data_out
);
reg[7:0]save_data;
reg[1:0]state;
always @(posedge clk or negedge rst)
begin 
    if(!rst)
        begin
            state <=2'd0;
            save_data<=8'd0;
            data_out<=8'd0;
        end
    else case(state)
        2'd0:   begin
                    if(start)
                        state <= state+1'd1;
                    else
                        state <= state;
                end
        2'd1:   begin
                    load;
                    state <= state + 1'd1;
                end
        2'd2:   begin
                    shift;
                    state <= state +1'd1;
                end
        2'd3:   begin
                    out(save_data,data_out);
                    state <= 2'd0;
                end      
         endcase
end
task load;
    begin 
        save_data <= data_in;
    end
endtask
task shift;
    begin   
        save_data <= save_data<<1;
    end
endtask
task out;
    input[7:0]a;
    input[7:0]b;
    begin
        b = a;
    end
endtask
endmodule

 

module function_test(
input   wire        clk,
input   wire        rst,
input   wire        start,
input   wire[7:0]   data_in,
output  reg [7:0]   data_out
);
reg[7:0]save_data;
reg[1:0]state;
always @(posedge clk or negedge rst)
begin 
    if(!rst)
        begin
            state <=2'd0;
            save_data<=8'd0;
            data_out<=8'd0;
        end
    else case(state)
        2'd0:   begin
                    if(start)
                        state <=state + 1'd1;
                    else
                        state <= state;
                end
        2'd1:   begin
                    save_data <= load_data(data_in);
                    state <= state + 1'd1;
                end
        2'd2:   begin
                    save_data <= shift(save_data);
                    state <= state+1'd1;
                end
        2'd3:   begin
                    data_out <= load_data(save_data);
                    state <= 2'd0;
                end
    endcase 
end

function [7:0]load_data;
    input [7:0]data;
    begin 
        load_data = data;
    end
endfunction
function [7:0] shift;
    input [7:0]shift_data;
    begin
        shift = shift_data << 1;
    end
endfunction
endmodule

6.