fpga_key_Led

最新推荐文章于 2023-05-24 21:03:28 发布

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最新推荐文章于 2023-05-24 21:03:28 发布

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分类专栏： fpga 文章标签： eda fpga

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module key_led
(
input sys_clk50,
input rst_n,
input [3:0] key,
output reg [3:0] led
);

reg [1:0] led_ctr;
reg [23:0] cnt;
// 定义计数器状态

always @(posedge sys_clk50 or negedge rst_n)begin
   if(!rst_n)
   cnt = 24'd0;
       else if(cnt < 24'd1000_0000)
   cnt <= cnt + 1'd1;
       else
   cnt <= 24'd0;
   end

   //定义状态计数器的状态

always @(posedge sys_clk50 or negedge rst_n) begin
   if(!rst_n)
   led_ctr <= 2'b0;
       else if(cnt == 24'd1000_0000)
           led_ctr <= led_ctr + 1'b1;
           else
           led_ctr <= led_ctr;
       end

       //定义led模式选择

always @(posedge sys_clk50 or negedge rst_n) begin
       if (!rst_n)
       led <= 4'b0000;
           else
           if(key[0] == 1'b0)
           case(led_ctr)
               2'b00: led <= 4'b1000;
               2'b01: led <= 4'b0100;
               2'b10: led <= 4'b0010;
               2'b11: led <= 4'b0001;
               endcase
           else
           if(key[1] == 1'b0)
                   case(led_ctr)
               2'b00: led <= 4'b0001;
               2'b01: led <= 4'b0010;
               2'b10: led <= 4'b0100;
               2'b11: led <= 4'b1000;
               endcase
               else
                   if(key[2] == 1'b0)
                       case(led_ctr)
                       2'b00: led <= 4'b1111;
2'b01: led <= 4'b0000;
2'b10: led <= 4'b1111;
2'b11: led <= 4'b0000;
                       endcase
               else
                   if(key[3] == 1'b0)
                       led <= 4'b1111;
                       else
                       led <= 4'b0000;
   end
   endmodule