VHDL编程中遇到该错误:
found ‘0’ definitions of operator “+”, cannot determine exact overloaded matching definition for “+”
原因:
可能是没有引入STD_LOGIC_UNSIGNED程序包
解决:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
…
12-29
5470
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