vhdl “0 definitions of operator”问题汇总与解决

标题vhdl “0 definitions of operator”问题汇总与解决

1.类型不匹配
如std_logic类型匹配boolean类型，示例如下
library IEEE;
use IEEE.std_logic_1164.all;

entity top is
generic( DATA_WIDTH : integer := 16;
ADDRESS_WIDTH : integer := 16);
port (
data_in : in STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
clk,rst: in STD_LOGIC;
cea,ceb:in STD_LOGIC;
data_out : out STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
end top;
architecture rtl of top is
begin
process(clk)
begin
if (rising_edge(clk)) then
if (rst=‘1’)then
data_out <=(others=>‘0’);
else
if(ceb=TRUE or cea)then
data_out <=data_in;
end if;
end if;
end if;
end process;
end rtl;

解决方案：将cea、ceb修改为cea,ceb:in boolean;

2.使用未声明的信号，示例如下：
library IEEE;
use IEEE.std_logic_1164.all;

entity top is
generic( DATA_WIDTH : integer := 16;
ADDRESS_WIDTH : integer := 16);
port (
data_in : in STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
clk,rst: in STD_LOGIC;
cea,ceb:in boolean;
data_out : out STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
end top;
architecture rtl of top is
begin
process(clk)
begin
if (rising_edge(clk)) then
if (rst=‘1’)then
data_out <=(others=>‘0’);
else
if(ceb1=TRUE or cea)then
data_out <=data_in;
end if;
end if;
end if;
end process;
end rtl;
上述示例中ceb1未声明，可以在architecture部分声明signal ceb1:boolean; 也可以在if语句中使用 if(ceb=TRUE or cea)then
3.STD_LOGIC_VECTOR与整数相加问题
library IEEE;
use IEEE.std_logic_1164.all;

entity top is
generic( DATA_WIDTH : integer := 16;
ADDRESS_WIDTH : integer := 16);
port (
data_in : in STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
clk,rst: in STD_LOGIC;
cea,ceb:in boolean;
data_out : out STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
end top;
architecture rtl of top is
begin
process(clk)
begin
if (rising_edge(clk)) then
if (rst=‘1’)then
data_out <=(others=>‘0’);
else
if(ceb=TRUE or cea)then
data_out <=data_in+10;
end if;
end if;
end if;
end process;
end rtl;
解决方案:
添加use IEEE.std_logic_unsigned.all;