醜奴兒_-CSDN博客

原创 Circuits-Sequential Logic-Counters

目录1、Four-bit binary counter2、Decade counter3、Decade counter again4、Slow decade counter5、Counter 1-126、Counter 10007、4-digit decimal counter8、12-hour clock参考资料：https://hdlbits.01xz.net/1、Four-bit binary counterBuild a 4-bit binary counter that counts fro

2021-07-22 10:36:47 173

原创 Circuits-Sequential Logic-Latches and Flip-Flops

目录1、D flip-flop2、D flip-flops3、DFF with reset4、DFF with reset value5、DFF with asynchronous reset6、DFF with byte enable7、D Latch8、DFF9、DFF10、DFF+gate11、MUX and DFF12、MUX and DFF13、DFFs and gates14、Create circuit from truth table15、Detect an edge16、Detect bo

2021-07-20 15:35:05 287

原创 Circuits-Combinational Logic-Karnaugh Map to circuit

目录1、3-variable2、4-variable3、4-variable4、4-variable5、Minimum SOP and POS6、Karnaugh map7、Karnaugh map8、K-map implemented with a multiplexer参考资料：https://hdlbits.01xz.net/1、3-variablemodule top_module( input a, input b, input c, output out

2021-07-19 10:33:09 113

原创 Circuits-Combinational Logic-Arithmetic Circuits

目录1、Half adder2、Full adder3、3-bit binary adder4、Adder5、Signed addition overflow6、100-bit binary adder7、4-digit BCD adder参考资料：https://hdlbits.01xz.net/1、Half adderCreate a half adder. A half adder adds two bits (with no carry-in) and produces a sum and c

2021-07-17 21:07:39 143

原创 Circuits-Combinational Logic-Multiplexers

目录1、2-to-1 multiplexer2、2-to-1 bus multiplexer3、9-to-1 multiplexer4、256-to-1 multiplexer5、256-to-1 4 bit multiplexer参考资料：https://hdlbits.01xz.net/1、2-to-1 multiplexerCreate a one-bit wide, 2-to-1 multiplexer. When sel=0, choose a. When sel=1, choose b.

2021-07-17 20:13:34 129

原创 Circuits-Combinational Logic-Basic Gates

目录1、Wire2、GND3、NOR4、Another gate5、Two gates6、More logic gates7、7420 chip8、Truth tables9、Two-bit equality10、Simple circuit A11、Simple circuit B12、Combine circuits A and B13、Ring or vibrate14、Thermostat15、3-bit population count16、Gates and vectors17、Even lon

2021-07-17 10:55:09 178

原创 Verilog Language-More Verilog Features

目录1、Conditional ternary operator2、Reduction operators3、Reduction: Even wider gates4、Combinational for-loop: Vector reversal 25、Combinational for-loop: 255-bit population count6、Generate for-loop: 100-bit binary adder 27、Generate for-loop: 100-digit BCD add

2021-07-16 15:06:39 159

原创 Verilog Language-Modules:Hierarchy

目录1、Modules2、Connecting ports by position3、Connecting ports by name4、Three modules5、Modules and vectors6、Adder17、Adder28、Carry-select adder9、Adder-subtractor1、ModulesConnecting Signals to Module PortsThere are two commonly-used methods to connect a wi

2021-06-18 20:09:40 414

原创 Verilog Language-Vectors

目录1、Vectors2、Vectors in more detail3、Vector part select4、Bitwise operators5、Four-input gates6、Vectors concatenation operator7、Vector reversal 18、Replication operator9、More replication1、VectorsVectors are used to group related signals using one name to ma

2021-06-17 19:30:34 169

原创 Verilog Language-Basics

目录1、Simple wire2、Four wires3、Inverter4、AND gate5、NOR gate6、XNOR gate7、Declaring wires8、7458 chip1、Simple wireUnlike physical wires, wires (and other signals) in Verilog are directional. This means information flows in only one direction, from (usually on

2021-06-17 16:51:26 117

原创 Verilog Language-Procedures

HDLBits个人学习笔记Verilog Language-Procedures目录Always blocks(combinational)Always blocks(clocked)If statementIf statement latchesCase statementPriority encoderPriority encoder with casezAvoiding latchesAlways blocks(combinational)Combinational always

2021-06-10 21:46:18 303

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