目录
1、Four-bit binary counter
Build a 4-bit binary counter that counts from 0 through 15, inclusive, with a period of 16. The reset input is synchronous, and should reset the counter to 0.
module top_module (
input clk,
input reset, // Synchronous active-high reset
output [3:0] q);
always@(posedge clk) begin
if(reset)
q <= 0;
else
q <= q + 1'b1;
end
endmodule
2、Decade counter
module top_module (
input clk,
input reset, // Synchronous active-high reset
output [3:0] q);
always@(posedge clk) begin
if(reset)
q <= 0;
else if(q >= 9)
q <= 0;
else
q <= q + 1'b1;
end
endmodule
3、Decade counter again
Make a decade counter that counts 1 through 10, inclusive. The reset input is synchronous, and should reset the counter to 1.
module top_module (
input clk,
input reset,
output [3:0] q);
always@(posedge clk) begin
if(reset)
q <= 4'b1;
else if(q >= 10)
q <= 1;
else
q <= q + 1'b1;
end
endmodule
4、Slow decade counter
Build a decade counter that counts from 0 through 9, inclusive, with a period of 10. The reset input is synchronous, and should reset the counter to 0. We want to be able to pause the counter rather than always incrementing every clock cycle, so the slowena input indicates when the counter should increment.
module top_module (
input clk,
input slowena,
input reset,
output [3:0] q);
always@(posedge clk) begin
if(reset)
q <= 0;
else if(slowena)begin
if(q >= 9)
q <= 0;
else
q <= q + 1'b1;
end
else
q <= q;
end
endmodule
5、Counter 1-12
Design a 1-12 counter with the following inputs and outputs:
1、Reset Synchronous active-high reset that forces the counter to 1
2、Enable Set high for the counter to run
3、Clk Positive edge-triggered clock input
4、Q[3:0] The output of the counter
5、c_enable, c_load, c_d[3:0] Control signals going to the provided 4-bit counter, so correct operation can be verified.
You have the following components available:
1、the 4-bit binary counter (count4) below, which has Enable and synchronous parallel-load inputs (load has higher priority than enable). The count4 module is provided to you. Instantiate it in your circuit.
2、logic gates
module top_module (
input clk,
input reset,
input enable,
output [3:0] Q,
output c_enable,
output c_load,
output [3:0] c_d
);
The c_enable, c_load, and c_d outputs are the signals that go to the internal counter’s enable, load, and d inputs, respectively. Their purpose is to allow these signals to be checked for correctness.
module top_module (
input clk,
input reset,
input enable,
output [3:0] Q,
output c_enable,
output c_load,
output [3:0] c_d
); //
count4 the_counter (clk, c_enable, c_load, c_d, Q);
assign c_enable = enable;
assign c_load = reset | ((Q == 12) && (enable == 1));
assign c_d = c_load ? 4'd1 : 4'd0;
endmodule
6、Counter 1000
From a 1000 Hz clock, derive a 1 Hz signal, called OneHertz, that could be used to drive an Enable signal for a set of hour/minute/second counters to create a digital wall clock. Since we want the clock to count once per second, the OneHertz signal must be asserted for exactly one cycle each second. Build the frequency divider using modulo-10 (BCD) counters and as few other gates as possible. Also output the enable signals from each of the BCD counters you use (c_enable[0] for the fastest counter, c_enable[2] for the slowest).
The following BCD counter is provided for you. Enable must be high for the counter to run. Reset is synchronous and set high to force the counter to zero. All counters in your circuit must directly use the same 1000 Hz signal.
module bcdcount (
input clk,
input reset,
input enable,
output reg [3:0] Q
);
module top_module (
input clk,
input reset,
output OneHertz,
output [2:0] c_enable
); //
wire [3:0] single,ten,hundred;
bcdcount counter0 (clk, reset, c_enable[0], single);
bcdcount counter1 (clk, reset, c_enable[1], ten);
bcdcount counter2 (clk, reset, c_enable[2], hundred);
assign c_enable = {(single==9) && (ten == 9), single== 9, 1'b1};
assign OneHertz = single==9 && ten == 9 && hundred==9;
endmodule
7、4-digit decimal counter
Build a 4-digit BCD (binary-coded decimal) counter. Each decimal digit is encoded using 4 bits: q[3:0] is the ones digit, q[7:4] is the tens digit, etc. For digits [3:1], also output an enable signal indicating when each of the upper three digits should be incremented.
module top_module (
input clk,
input reset, // Synchronous active-high reset
output [3:1] ena,
output [15:0] q);
//个位数计数
always@(posedge clk) begin
if(reset)
q[3:0] <= 0;
else if(q[3:0] >= 9)
q[3:0] <= 0;
else
q[3:0] <= q[3:0] + 1'b1;
end
//十位数计数
always@(posedge clk) begin
if(reset)
q[7:4] <= 0;
else if((q[7:4] >= 9) && (q[3:0] == 9))
q[7:4] <= 0;
else
if(q[3:0] == 9)
q[7:4] <= q[7:4] + 1'b1;
else
q[7:4] <= q[7:4];
end
//百位数计数
always@(posedge clk) begin
if(reset)
q[11:8] <= 0;
else if((q[11:8] >= 9) && (q[7:4] == 9) && (q[3:0] == 9))
q[11:8] <= 0;
else
if((q[7:4] == 9) && (q[3:0] == 9))
q[11:8] <= q[11:8] + 1'b1;
else
q[11:8] <= q[11:8];
end
//千位数计数
always@(posedge clk) begin
if(reset)
q[15:12] <= 0;
else if((q[15:12] >= 9) && (q[11:8] == 9) && (q[7:4] == 9) && (q[3:0] == 9) )
q[15:12] <= 0;
else
if((q[7:4] == 9) && (q[3:0] == 9) && (q[11:8] == 9))
q[15:12] <= q[15:12] + 1'b1;
else
q[15:12] <= q[15:12];
end
assign ena[3:1] = {(q[11:8]==9) && (q[7:4] == 9) && (q[3:0] == 9), (q[7:4] == 9) && (q[3:0] == 9), q[3:0] == 9};
endmodule
8、12-hour clock
Create a set of counters suitable for use as a 12-hour clock (with am/pm indicator). Your counters are clocked by a fast-running clk, with a pulse on ena whenever your clock should increment (i.e., once per second).
reset resets the clock to 12:00 AM. pm is 0 for AM and 1 for PM. hh, mm, and ss are two BCD (Binary-Coded Decimal) digits each for hours (01-12), minutes (00-59), and seconds (00-59). Reset has higher priority than enable, and can occur even when not enabled.
The following timing diagram shows the rollover behaviour from 11:59:59 AM to 12:00:00 PM and the synchronous reset and enable behaviour.
module top_module(
input clk,
input reset,
input ena,
output pm,
output [7:0] hh,
output [7:0] mm,
output [7:0] ss);
//sec
always@(posedge clk)
if(reset)
ss[3:0] <= 0;
else if(ena) begin
if(ss[3:0]>=4'd9)
ss[3:0] <= 0;
else
ss[3:0] <= ss[3:0] + 1'b1;
end
else
ss[3:0] <= ss[3:0];
always@(posedge clk)
if(reset)
ss[7:4] <= 0;
else if(ena) begin
if((ss[7:4]>=4'd5) && (ss[3:0]==4'd9))
ss[7:4] <= 0;
else if(ss[3:0]==4'd9)
ss[7:4] <= ss[7:4] + 1'b1;
else
ss[7:4] <= ss[7:4];
end
else
ss[7:4] <= ss[7:4];
//minute
always@(posedge clk)
if(reset)
mm[3:0] <= 0;
else if(ena) begin
if((mm[3:0]>=4'd9 && (ss[7:4]>=4'd5) && (ss[3:0]==4'd9)))
mm[3:0] <= 0;
else if((ss[3:0]==4'd9) && (ss[7:4]==4'd5))
mm[3:0] <= mm[3:0] + 1'b1;
else
mm[3:0] <= mm[3:0];
end
else
mm[3:0] <= mm[3:0];
always@(posedge clk)
if(reset)
mm[7:4] <= 0;
else if(ena) begin
if((mm[7:4]>=4'd5 && mm[3:0]==4'd9 && (ss[7:4]>=4'd5) && (ss[3:0]==4'd9)))
mm[7:4] <= 0;
else if((ss[3:0]==4'd9) && (ss[7:4]==4'd5) && (mm[3:0]==4'd9))
mm[7:4] <= mm[7:4] + 1'b1;
else
mm[7:4] <= mm[7:4];
end
else
mm[7:4] <= mm[7:4];
//hour
always@(posedge clk)
if(reset)
hh[3:0] <= 2;
else if(ena) begin
if((hh[3:0]>=4'd9) && (ss[7:4]>=4'd5) && (ss[3:0]==4'd9) && (mm[7:4]==4'd5) && (mm[3:0]==4'd9))
hh[3:0] <= 0;
else if((hh[7:4]==4'd1) && (hh[3:0]==4'd2) && (hh[3:0]==4'd2) && (ss[7:4]>=4'd5) && (ss[3:0]==4'd9) && (mm[7:4]==4'd5) && (mm[3:0]==4'd9))
hh[3:0] <= 1;
else if((ss[3:0]==4'd9) && (ss[7:4]==4'd5) && (mm[7:4]==4'd5) && (mm[3:0]==4'd9))
hh[3:0] <= hh[3:0] + 1'b1;
else
hh[3:0] <= hh[3:0];
end
else
hh[3:0] <= hh[3:0];
always@(posedge clk)
if(reset)
hh[7:4] <= 1;
else if(ena) begin
if((hh[7:4]==4'd1) && (hh[3:0]==4'd2) && (ss[7:4]>=4'd5) && (ss[3:0]==4'd9) && (mm[7:4]==4'd5) && (mm[3:0]==4'd9))
hh[7:4] <= 4'd0;
else if((hh[7:4]==4'd0) && (hh[3:0]==4'd9) && (ss[7:4]>=4'd5) && (ss[3:0]==4'd9) && (mm[7:4]==4'd5) && (mm[3:0]==4'd9))
hh[7:4] <= 4'd1;
else
hh[7:4] <= hh[7:4];
end
else
hh[7:4] <= hh[7:4];
//AM?PM
always@(posedge clk)
if(reset)
pm <= 0;
else begin
if((hh[7:4] == 4'd1) && (hh[3:0]==4'd1) && (ss[3:0]==4'd9) && (ss[7:4]==4'd5) && (mm[3:0]==4'd9) && (mm[7:4]==4'd5))
pm <= ~pm;
else
pm <= pm;
end
endmodule
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