Verilog Language-Basics

1、Simple wire

Unlike physical wires, wires (and other signals) in Verilog are directional. This means information flows in only one direction, from (usually one) source to the sinks (The source is also often called a driver that drives a value onto a wire).

Create a module with one input and one output that behaves like a wire.

module top_module( input in, output out );
	
	assign out = in;
	// Note that wires are directional, so "assign in = out" is not equivalent.
	
endmodule

2、Four wires

When you have multiple assign statements, the order in which they appear in the code does not matter.

Create a module with 3 inputs and 4 outputs that behaves like wires that makes these connections:
a -> w
b -> x
b -> y
c -> z

module top_module (
	input a,
	input b,
	input c,
	output w,
	output x,
	output y,
	output z  );
	
	assign w = a;
	assign x = b;
	assign y = b;
	assign z = c;

	// If we're certain about the width of each signal, using 
	// the concatenation operator is equivalent and shorter:
	// assign {w,x,y,z} = {a,b,b,c};
	
endmodule

3、Inverter

Create a module that implements a NOT gate.

module top_module(
	input in,
	output out
);
	
	assign out = ~in;
	
endmodule

4、AND gate

As you might expect, a wire cannot have more than one driver (what is its logic level if there is?), and a wire that has no drivers will have an undefined value (often treated as 0 when synthesizing hardware).
不能被多次赋值？

Create a module that implements an AND gate.

module top_module( 
    input a, 
    input b, 
    output out );
	
    assign out = a & b;
    
endmodule

5、NOR gate

Create a module that implements a NOR gate. A NOR gate is an OR gate with its output inverted. A NOR function needs two operators when written in Verilog.

module top_module( 
    input a, 
    input b, 
    output out );
    
    assign out = ~(a|b);

endmodule

6、XNOR gate

Create a module that implements an XNOR gate.

module top_module( 
    input a, 
    input b, 
    output out );
    
    assign out = ~(a^b);

endmodule

7、Declaring wires

Implement the following circuit. Create two intermediate wires (named anything you want) to connect the AND and OR gates together. Note that the wire that feeds the NOT gate is really wire out, so you do not necessarily need to declare a third wire here. Notice how wires are driven by exactly one source (output of a gate), but can feed multiple inputs.

module top_module (
	input a,
	input b,
	input c,
	input d,
	output out,
	output out_n );
	
	wire w1, w2;		// Declare two wires (named w1 and w2)
	assign w1 = a&b;	// First AND gate
	assign w2 = c&d;	// Second AND gate
	assign out = w1|w2;	// OR gate: Feeds both 'out' and the NOT gate

	assign out_n = ~out;	// NOT gate
	
endmodule

8、7458 chip

module top_module ( 
    input p1a, p1b, p1c, p1d, p1e, p1f,
    output p1y,
    input p2a, p2b, p2c, p2d,
    output p2y );
    
    assign p1y = (p1a & p1c & p1b)|(p1f & p1e & p1d);
    assign p2y = (p2c & p2d)|(p2a & p2b);

endmodule

module top_module ( 
    input p1a, p1b, p1c, p1d, p1e, p1f,
    output p1y,
    input p2a, p2b, p2c, p2d,
    output p2y );
    
    wire p3y = (p1f & p1e & p1d);
    wire p4y = (p1a & p1c & p1b);
    wire p5y = (p2c & p2d);
    wire p6y = (p2a & p2b);
    assign p1y = p3y|p4y;
    assign p2y = p5y|p6y;
    
endmodule

参考资料：https://hdlbits.01xz.net/