Circuits-Combinational Logic-Karnaugh Map to circuit

1、3-variable

module top_module(
    input a,
    input b,
    input c,
    output out  ); 
    assign out = ~((~a)&(~b)&(~c));
endmodule

2、4-variable

module top_module(
    input a,
    input b,
    input c,
    input d,
    output out  ); 
    assign out = (~a)&(~d) | (~a)&(~b)&(~c) | (~a)&b&c | (~b)&(~c) | a&c&d;
endmodule

3、4-variable

module top_module(
    input a,
    input b,
    input c,
    input d,
    output out  ); 
    assign out = a | ((~a)&(~b)&c);
endmodule

4、4-variable

module top_module(
    input a,
    input b,
    input c,
    input d,
    output out  ); 
    assign out = (~a&b&~c&~d) | (a&~b&~c&~d) | 
        		 (~a&~b&~c&d) | (a&b&~c&d)   | 
       			 (~a&b&c&d)   | (a&~b&c&d)   | 
        		 (~a&~b&c&~d) | (a&b&c&~d);
endmodule

5、Minimum SOP and POS

A single-output digital system with four inputs (a,b,c,d) generates a logic-1 when 2, 7, or 15 appears on the inputs, and a logic-0 when 0, 1, 4, 5, 6, 9, 10, 13, or 14 appears. The input conditions for the numbers 3, 8, 11, and 12 never occur in this system. For example, 7 corresponds to a,b,c,d being set to 0,1,1,1, respectively.

SOP(Sum of Product)：(c&d) | (~ a&~b&c)
POS(Product of Sum)： ~ ((~ c|~d) & (a|b|~c))

module top_module (
    input a,
    input b,
    input c,
    input d,
    output out_sop,
    output out_pos
); 
    assign out_sop = (c&d) | (~a&~b&c);
    assign out_pos = ~((~c|~d) & (a|b|~c));
endmodule

6、Karnaugh map

module top_module (
    input [4:1] x, 
    output f );
    assign f = (~x[1] & x[3]) | (x[2] & x[4]);
endmodule

7、Karnaugh map

module top_module (
    input [4:1] x,
    output f
); 

    assign f = ~x[2]&~x[4] | ~x[1]&x[3] | x[2]&x[3]&x[4];
    
endmodule

8、K-map implemented with a multiplexer

module top_module (
    input c,
    input d,
    output [3:0] mux_in
); 
    always@(*) begin
        case({c,d})
            2'b00:mux_in = 4'b0100;
            2'b01:mux_in = 4'b0001;
            2'b11:mux_in = 4'b1001;
            default:mux_in = 4'b0101;
        endcase
    end
        
endmodule

参考资料：https://hdlbits.01xz.net/