Verilog Language-More Verilog Features

1、Conditional ternary operator

Verilog has a ternary conditional operator ( ? : ) much like C:(condition ? if_true : if_false)

module top_module (
    input [7:0] a, b, c, d,
    output [7:0] min);//
    
    wire [7:0] m1;
    wire [7:0] m2;
    assign m1 = (a < b) ? a : b;
    assign m2 = (c < d) ? c : d;
    assign min = (m1 < m2) ? m1 : m2;

endmodule

2、Reduction operators

The reduction operators can do AND, OR, and XOR of the bits of a vector, producing one bit of output:
& a[3:0] // AND: a[3]&a[2]&a[1]&a[0]. Equivalent to (a[3:0] == 4’hf)
| b[3:0] // OR: b[3]|b[2]|b[1]|b[0]. Equivalent to (b[3:0] != 4’h0)
^ c[2:0] // XOR: c[2]^c[1]c[0]
These are unary operators that have only one operand (similar to the NOT operators ! and ~). You can also invert the outputs of these to create NAND, NOR, and XNOR gates, e.g., (~& d[7:0]).

module top_module (
    input [7:0] in,
    output parity); 
	assign parity = ^in;
endmodule

3、Reduction: Even wider gates

Build a combinational circuit with 100 inputs, in[99:0].
There are 3 outputs:
out_and: output of a 100-input AND gate.
out_or: output of a 100-input OR gate.
out_xor: output of a 100-input XOR gate.

module top_module( 
    input [99:0] in,
    output out_and,
    output out_or,
    output out_xor 
);
	assign out_and 	= & in;
    assign out_or 	= | in;
    assign out_xor 	= ^ in;
endmodule

4、Combinational for-loop: Vector reversal 2

Given a 100-bit input vector [99:0], reverse its bit ordering.

module top_module( 
    input [99:0] in,
    output [99:0] out
);
    integer i;
    always@(*) begin
        for(i=0;i<100;i=i+1)
            out[i] = in[99-i];
    end
        
endmodule

5、Combinational for-loop: 255-bit population count

A “population count” circuit counts the number of '1’s in an input vector. Build a population count circuit for a 255-bit input vector.

module top_module( 
    input [254:0] in,
    output [7:0] out );
	integer i;
    always@(*) begin
    	out = 0;
        for(i=0;i<255;i=i+1)
            out = out + in[i];
    end
endmodule

6、Generate for-loop: 100-bit binary adder 2

Create a 100-bit binary ripple-carry adder by instantiating 100 full adders. The adder adds two 100-bit numbers and a carry-in to produce a 100-bit sum and carry out. To encourage you to actually instantiate full adders, also output the carry-out from each full adder in the ripple-carry adder. cout[99] is the final carry-out from the last full adder, and is the carry-out you usually see.

module top_module( 
    input [99:0] a, b,
    input cin,
    output [99:0] cout,
    output [99:0] sum );
    
    assign cout[0] 	= a[0]&b[0] | a[0]&cin | b[0]&cin;
    assign sum[0] 	= a[0]^b[0]^cin;
    integer i;
    always@(*) begin
        for(i=1;i<100;i=i+1) begin
            cout[i] = a[i]&b[i] | a[i]&cout[i-1] | b[i]&cout[i-1];
            sum[i] 	= a[i]^b[i]^cout[i-1];
        end    
    end

endmodule

7、Generate for-loop: 100-digit BCD adder

You are provided with a BCD one-digit adder named bcd_fadd that adds two BCD digits and carry-in, and produces a sum and carry-out.
module bcd_fadd {
input [3:0] a,
input [3:0] b,
input cin,
output cout,
output [3:0] sum );
Instantiate 100 copies of bcd_fadd to create a 100-digit BCD ripple-carry adder. Your adder should add two 100-digit BCD numbers (packed into 400-bit vectors) and a carry-in to produce a 100-digit sum and carry out.

module top_module( 
    input [399:0] a, b,
    input cin,
    output cout,
    output [399:0] sum );
    
    wire [99:0] cout_s;
    assign cout = cout_s[99];
    bcd_fadd add1(
        .a		(a[3:0]),
        .b		(b[3:0]),
        .cin	(cin),
        .cout	(cout_s[0]),
        .sum	(sum[3:0])
    );
    genvar i;
    generate for(i=1;i<100;i=i+1) 
        begin:loop
            bcd_fadd add2(
                .a		(a[4*i+3:4*i]),
                .b		(b[4*i+3:4*i]),
                .cin	(cout_s[i-1]),
                .cout	(cout_s[i]),
                .sum	(sum[4*i+3:4*i])
            );
        end
    endgenerate
endmodule

参考资料：https://hdlbits.01xz.net/