牛客网Verilog刷题——VL16

题目

  请使用2片该优先编码器Ⅰ及必要的逻辑电路实现16线-4线优先编码器。优先编码器Ⅰ的真值表和代码已给出。可将优先编码器Ⅰ的代码添加到本题答案中，并例化。优先编码器Ⅰ的代码如下：

module encoder_83(
   input      [7:0]       I   ,
   input                  EI  ,
   
   output wire [2:0]      Y   ,
   output wire            GS  ,
   output wire            EO    
);
assign Y[2] = EI & (I[7] | I[6] | I[5] | I[4]);
assign Y[1] = EI & (I[7] | I[6] | ~I[5]&~I[4]&I[3] | ~I[5]&~I[4]&I[2]);
assign Y[0] = EI & (I[7] | ~I[6]&I[5] | ~I[6]&~I[4]&I[3] | ~I[6]&~I[4]&~I[2]&I[1]);

assign EO = EI&~I[7]&~I[6]&~I[5]&~I[4]&~I[3]&~I[2]&~I[1]&~I[0];

assign GS = EI&(I[7] | I[6] | I[5] | I[4] | I[3] | I[2] | I[1] | I[0]);
//assign GS = EI&(| I);
         
endmodule

  下表是8线-3线优先编码器Ⅰ的功能表。

信号	类型	输入/输出	位宽
A	wire	Intput	15
EI	wire	Intput	1
L	wire	Output	4
GS	wire	Output	1
EO	wire	Output	1

答案

`timescale 1ns/1ns
module encoder_83(
   input      [7:0]       I   ,
   input                  EI  ,
   
   output wire [2:0]      Y   ,
   output wire            GS  ,
   output wire            EO    
);
assign Y[2] = EI & (I[7] | I[6] | I[5] | I[4]);
assign Y[1] = EI & (I[7] | I[6] | ~I[5]&~I[4]&I[3] | ~I[5]&~I[4]&I[2]);
assign Y[0] = EI & (I[7] | ~I[6]&I[5] | ~I[6]&~I[4]&I[3] | ~I[6]&~I[4]&~I[2]&I[1]);

assign EO = EI&~I[7]&~I[6]&~I[5]&~I[4]&~I[3]&~I[2]&~I[1]&~I[0];

assign GS = EI&(I[7] | I[6] | I[5] | I[4] | I[3] | I[2] | I[1] | I[0]);
//assign GS = EI&(| I);
         
endmodule

module encoder_164(
   input      [15:0]      A   ,
   input                  EI  ,
   
   output wire [3:0]      L   ,
   output wire            GS  ,
   output wire            EO    
);

wire EO_1,EO_2;
wire GS_1,GS_2;
wire [2:0] Y1,Y2;

assign EO = EO_2;
assign GS = GS_1 || GS_2;
assign L[3] = GS_1;
assign L[2] = Y1[2] | Y2[2];
assign L[1] = Y1[1] | Y2[1];
assign L[0] = Y1[0] | Y2[0];

encoder_83 encoder_83_inst_1(
   .I   (A[15:8]),
   .EI  (EI),
   
   .Y   (Y1),
   .GS  (GS_1),
   .EO  (EO_1)  
);

encoder_83 encoder_83_inst_2(
   .I   (A[7:0]),
   .EI  (EO_1),
   
   .Y   (Y2),
   .GS  (GS_2),
   .EO  (EO_2)  
);

endmodule