目录
Karnaugh Map to circuit(卡诺图到电路)
Arithmetic Circuits(算数电路)
1.Bcdadd4
You are provided with a BCD (binary-coded decimal) one-digit adder named bcd_fadd that adds two BCD digits and carry-in, and produces a sum and carry-out.
为您提供了一个名为bcd_fadd的 BCD(二进制编码十进制)一位数加法器,它将两个 BCD 数字和进位相加,并产生一个总和和进位。
module top_module(
input [15:0] a, b,
input cin,
output cout,
output [15:0] sum );
wire [2:0] cin_in;
bcd_fadd U1(a[3:0], b[3:0], cin, cin_in[0], sum[3:0]);
bcd_fadd U2(a[7:4], b[7:4], cin_in[0], cin_in[1], sum[7:4]);
bcd_fadd U3(a[11:8], b[11:8], cin_in[1], cin_in[2], sum[11:8]);
bcd_fadd U4(a[15:12], b[15:12], cin_in[2], cout, sum[15:12]);
endmodule
Karnaugh Map to circuit(卡诺图到电路)
1.Kmap1
module top_module(
input a,
input b,
input c,
output out );
assign out = a|b|c;
endmodule
2.Kmap2
module top_module(
input a,
input b,
input c,
input d,
output out );
assign out = (~a&~d)|(~b&~c)|(b&c&d)|(a&c&d);
endmodule
3.Kmap3
module top_module(
input a,
input b,
input c,
input d,
output out );
assign out = a|(~b&c);
endmodule
4.Kmap4
module top_module(
input a,
input b,
input c,
input d,
output out );
assign out = ((a^b)&~(c^d))|(~(a^b)&(c^d));
endmodule
5.Exams/ece241 2013 q2
A single-output digital system with four inputs (a,b,c,d) generates a logic-1 when 2, 7, or 15 appears on the inputs, and a logic-0 when 0, 1, 4, 5, 6, 9, 10, 13, or 14 appears. The input conditions for the numbers 3, 8, 11, and 12 never occur in this system. For example, 7 corresponds to a,b,c,d being set to 0,1,1,1, respectively.
Determine the output out_sop in minimum SOP form, and the output out_pos in minimum POS form.
- SOP标准式:找出真值表中所有输出为1的表项,按照输入的情况,为1用变量表示,为0则用反变量表示,得出若干乘积项,然后求和。
- POS标准式:找出真值表中所有输出为0的表项,按照输入的情况,为1用反变量表示,为0则用原变量表示,得出若干求和项,然后求积。
module top_module (
input a,
input b,
input c,
input d,
output out_sop,
output out_pos
);
assign out_sop = c&d | ~a&~b&c;
assign out_pos = ~(~c | a&~b | b&~d);
endmodule
6.Exams/m2014 q3
module top_module (
input [4:1] x,
output f );
assign f = ~x[1]&x[3] | x[2]&x[4];
endmodule
7.Exams/m2012 q1g
module top_module (
input [4:1] x,
output f
);
assign f = ~x[1]&x[3] | ~x[2]&~x[4] | x[2]&x[3]&x[4];
endmodule
8.Exams/ece241 2014 q3
module top_module (
input c,
input d,
output [3:0] mux_in
);
assign mux_in[0] = d | c;
assign mux_in[1] = 0;
assign mux_in[2] = ~d;
assign mux_in[3] = c&d;
endmodule