Systemverilog::随机指定范围方法

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前言

Systemverilog 随机到指定范围的几种方法

1. constrain + rand

constraint : 权重分布
:= 数值范围内每一个值的权重十相等的
：/ 权重要均分到数值范围内的每一个值

// 简单约束
rand int in src, dst;
constraint c_in{
	in>16;
	in<20;
}
// 权重约束
constraint c_dist{
	src dist{0:=40,[1:3]:=60};
// src = 0: weight = 40/220
// src = 1: weight = 60/220
// src = 2: weight = 60/220
......
// inside 约束
rand bit[6:0] b;
constrain b_range{
	b inside{[$:4],[20:$]}; // 0<=b<=4 || 20<=b<=127
}

2. randomize方法

real clk_sysy_div_val;
real clk_aux_div_val;
assert(std::randomize(clk_sys_div_val) with {clk_sys_div_val inside {0, 1, 2, 4, 8, 16};}); 
assert(std::randomize(clk_aux_div_val) with {clk_aux_div_val inside {25, 50, 100};});  

3.randcase 方法

logic[31:0] cfg1;
delay_ns(1000);
randcase
10:begin //PLL_CLK 1000 MHZ
	cfg1[5:0]  = 6'h0; //p
end
10:begin //PLL_CLK 1050 MHZ
    cfg0[14:5]  = 10'h98 ; //mint
end    
 endcase