systemverilog std::randomize()

要随机产生一个4bit的 -1 ~ -7的数:
val = $urandom_range(-1,-7);

要随机产生一个4bit的 0 ~ -7的数:
val = $urandom_range(-0,-7); // 这样写错误


需要写成
std::randomize(val) with { val inside {0,[9:15]};};
#val变量中4个bit为1,其余为0.
bit [100:0] val
void'(std::randomize(val) with { $countones(val) inside {4} ; }); 

#val变量中4个1,其余为0. (绿皮书6.13.2节 书本错误)
bit val[10];
void'(std::randomize(val) with { val.sum() with (int'(item)) == 4'h4; }); ## item含义参考绿皮书p35 



如下示例和仿真器有关:
#十个数相加和为50,每个数都小于7
第一种写法:
bit [5:0] d1[10];
void'(std::randomize(d1) with {d1.sum() with ((item<7) * item)  == 50;});

第二种写法:
bit [5:0] d1[10];
void'(std::randomize(d1) with {d1.sum() with ((item<7) ? item : 0)  == 50;});

#随机出任意5个小于10的数
bit [5:0] d1[10];
void'(std::randomize(d1) with {d1.sum() with (int'(item<10 ))  == 5;}); #需要加上int

参考:

https://www.cnblogs.com/-9-8/p/4414449.html

http://www.itkeyword.com/doc/1250864225704845x672/difference-between-stdrandomize-and-class-based-randomize

Systemverilog randsequence 中的 rand join 使用方法

Example:

constraint cons_value{
    num1 < 1024;
    num2 > 0;
    (rd_flag == 1'b1) -> data_queue.size == num1 - num1;
    data_queue.sum == 1024;
    if(mode == 1'b0) { num dist {[1:10]:/20,[11:12]:/60};}
    if(gen_mode == 1){ 
        sim inside {0,1,2};
        (sim == 2) -> a == 4;   
    } else if (gen_mode == 4) {
        b ==5;
    }
    foreach(data_queue[i]){
        data_queue[i] inside {[0:data]};
        if(wr_flag == 1) {
            data_queue[i] % 9 == 0;
        }
    }
}

assert(std::randomize(val_a) with {val_a inside {[0:10],[100:1000]};};
sucess = std::randomize(val_1,val_2,val_3) with { 
   val_1 inside { A ,B ,C};
   val_2 dist { A := 2 ,B := 5 ,C := 4 };
   val_3 inside {[0:{32{1'b}}]}; 
};

if(  sucess == 0 ) begin
   `uvm_fatal("TEST", " randomization failed")
end

class rand_value extends uvm_sequence_item;
    randc int value;
    constraint c_value {value inside {[1:16]};}
endclass

rand_value r_value;
r_value = new();
repeat(16) begin
    //r_value = new(); #放在内部错误,无法遍历到
    r_value.randomize();
    $display("value:%0d",r_value.vaule);
end

post_randomize()

post_randomize 用于有先后关系的随机化

class Package_Gen;
    rand bit [7:0] value[];
    rand bit [7:0] index[];
    
    package_type cmd_s;

    constraint cons_package {
                             value.size inside {[0:8]};
                             index.size inside {[0:1024]};
                             index.size % 16 == 0;
                            }

    function void post_randomize();
        cmd_s.block_value = value.size;
        cmd_s.index_value = index.size;
    endfunciton
endclass
class c1;
rand int randnum;
int hist[$];
constraint cstr1 {randnum inside {[0:10]};};
constraint cstr2 {!(randnum inside {hist});};
function void post_randomize();
  hist.push_back(randnum);
endfunction
endclass

module m1;

initial begin
c1 i1;
i1 = new();
  repeat(10) begin
    assert(i1.randomize());
    $display("m1::proc2.i1 randnum %0d", i1.randnum);
  end
end
endmodule

动态数组最后一个元素,约束为固定值。数组大小未知。

rand int some_dynamic_array[];
constraint last_elem_c {
  foreach(some_dynamic_array[i])
    if (i == some_dynamic_array.size() - 1)
      some_dynamic_array[i] == 5;
}

固定值包含在数组中(inside是双向作用的)

constraint contains_c {
  2 inside { some_dynamic_array };
}

  数组中不包含某个值

constraint not_contains_c {
  !( 5 inside { some_dynamic_array });
}
Contents Part One: Design and Verification Constructs 1. Overview.................................................................................................................................................... 2 1.1 Scope................................................................................................................................................ 2 1.2 Purpose............................................................................................................................................. 2 1.3 Merger of IEEE Std 1364-2005 and IEEE Std 1800-2005.............................................................. 3 1.4 Special terms.................................................................................................................................... 3 1.5 Conventions used in this standard ................................................................................................... 3 1.6 Syntactic description........................................................................................................................ 4 1.7 Use of color in this standard ............................................................................................................ 5 1.8 Contents of this standard.................................................................................................................. 5 1.9 Deprecated clauses........................................................................................................................... 8 1.10 Examples.......................................................................................................................................... 8 1.11 Prerequisites..................................................................................................................................... 8 2. Normative references ................................................................................................................................. 9 3. Design and verification building blocks .................................................................................................. 11 3.1 General........................................................................................................................................... 11 3.2 Design elements ............................................................................................................................. 11 3.3 Modules ......................................................................................................................................... 11 3.4 Programs ........................................................................................................................................ 12 3.5 Interfaces........................................................................................................................................ 13 3.6 Checkers......................................................................................................................................... 14 3.7 Primitives ....................................................................................................................................... 14 3.8 Subroutines .................................................................................................................................... 14 3.9 Packages......................................................................................................................................... 14 3.10 Configurations ............................................................................................................................... 15 3.11 Overview of hierarchy ................................................................................................................... 15 3.12 Compilation and elaboration.......................................................................................................... 16 3.13 Name spaces .................................................................................................................................. 18 3.14 Simulation time units and precision............................................................................................... 19 4. Scheduling semantics............................................................................................................................... 23 4.1 General........................................................................................................................................... 23 4.2 Execution of a hardware model and its verification environment ................................................. 23 4.3 Event simulation ............................................................................................................................ 23 4.4 The stratified event scheduler ........................................................................................................ 24 4.5 The SystemVerilog simulation reference algorithm...................................................................... 29 4.6 Determinism................................................................................................................................... 29 4.7 Nondeterminism............................................................................................................................. 30 4.8 Race conditions.............................................................................................................................. 30 4.9 Scheduling implication of assignments ......................................................................................... 30 4.10 The PLI callback control points..................................................................................................... 32
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