HDLBits Fsm hdlc

1、这个题一步到位，一次成功还是挺简单的理清思路，想好状态是怎么变化的就可以了。

2、值得注意的是error那个标志如果in不为0的话，会一直为1；

完整代码如下：

module top_module(
    input clk,
    input reset,    // Synchronous reset
    input in,
    output disc,
    output flag,
    output err);
    
    parameter ready=0,A=1,B=2,C=3,D=4,E=5,F=6,Dic=9,Flag=7,ERR=8;
    reg [3:0]state, next_state;
    always@(*)begin
        case(state)
            ready:next_state=in?A:ready;
            A:next_state=in?B:ready;
             B:next_state=in?C:ready;
             C:next_state=in?D:ready;
             D:next_state=in?E:ready;
             E:next_state=in?F:Dic;
             F:next_state=in?ERR:Flag;
             Dic:next_state=in?A:ready;
             Flag:next_state=in?A:ready;
             ERR:next_state=in?ERR:ready;          
        endcase
    end
    
    always@(posedge clk)begin
        if(reset)
            state<=ready;
        else
            state<=next_state;      
    end
    assign disc=(state==Dic);
	assign flag=(state==Flag);
    assign err=(state==ERR);
endmodule