Verilog HDL基础
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[HDLBits] 习题记录(2)
4、Create a module with 3 inputs and 4 outputs that behaves like wires that makes these connections: a -> w b -> x b -> y c -> z 创建一个有3个输入端口和四个输出端口的模块,并且按照a -> w;b -> x;b -> y;c -> z,来连接输入和输出端口。 module top_module( input a,b,c,原创 2021-06-21 00:23:22 · 157 阅读 · 0 评论 -
[HDLBits] 习题记录(1)
1、We’re going to start with a small bit of HDL to get familiar with the interface used by HDLBits. Here’s the description of the circuit you need to build for this exercise: Build a circuit with no inputs and one output. That output should always drive 1 (原创 2021-06-15 00:26:37 · 270 阅读 · 1 评论