[HDLBits] 习题记录（1）

1、We’re going to start with a small bit of HDL to get familiar with the interface used by HDLBits. Here’s the description of the circuit you need to build for this exercise:

Build a circuit with no inputs and one output. That output should always drive 1 (or logic high).
写一个模块，没有输入，只有一个输出，且一直输出高电平。

module top_module(
output one
);

    assign one = 1'b1;
    
endmodule

2、Build a circuit with no inputs and one output that outputs a constant 0
写一个模块，没有输入，只有一个输出，且一直输出低电平。

module top_module(
    output zero
);

assign zero=1'b0;

endmodule

3、Create a module with one input and one output that behaves like a wire.
写一个模块，只有一个输入，只有一个输出，将输出与输入像线一样连接起来。

module top_module(
input in, 

output out 
);

assign out=in;

endmodule

Unlike physical wires, wires (and other signals) in Verilog are directional. This means information flows in only one direction, from (usually one) source to the sinks (The source is also often called a driver that drives a value onto a wire). In a Verilog “continuous assignment” (), the value of the signal on the right side is driven onto the wire on the left side. The assignment is “continuous” because the assignment continues all the time even if the right side’s value changes. A continuous assignment is not a one-time event. assign left_side = right_side;

conclusion：

1. assign赋值有方向，例如assign left_side = right_side;只能将右边的值赋值给左边。
2. 赋值是连续的，当右边的值发生改变，左边会跟着做相应的变化，并不是值赋值一次，而是一直赋值。