蜂鸣器电子琴 Verilog

最新推荐文章于 2023-10-27 11:44:38 发布

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最新推荐文章于 2023-10-27 11:44:38 发布

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分类专栏：电子设计自动化文章标签： verilog

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蜂鸣器

电子琴


module beep
(
   CLK_50M,RST_N,KEY,
   BEEP
);

input 		CLK_50M;
input			RST_N;
input [7:0] KEY;

output 		BEEP;

//内部接口申明

reg	[19:0]	time_cnt;
reg	[19:0]	time_cnt_n;
reg	[15:0]	freq;
reg				beep_reg;
reg				beep_reg_n;

always@(posedge CLK_50M or negedge RST_N)
begin
   if(!RST_N)
   	time_cnt<=1'b0;
   else
   	time_cnt<=time_cnt_n;
end

always@(*)
begin
   if(time_cnt ==freq)
   	time_cnt_n=1'b0;
   else
   	time_cnt_n=time_cnt+1'b1;
end

always@(posedge CLK_50M or negedge RST_N)
begin
   if(!RST_N)
   	beep_reg<=1'b0;
   else
   	beep_reg<=beep_reg_n;
end

always@(*)
begin
   if(time_cnt==freq)
   	beep_reg_n=~beep_reg;
   else
   	beep_reg_n=beep_reg;
end

always@(KEY)
begin
   case(KEY)
   	8'b00000001:freq<=16'd47774;
   	8'b00000010:freq<=16'd42568;
   	8'b00000100:freq<=16'd37919;
   	8'b00001000:freq<=16'd35791;
   	8'b00010000:freq<=16'd31888;
   	8'b00100000:freq<=16'd28409;
   	8'b01000000:freq<=16'd25309;
   	8'b10000000:freq<=16'd23889;
   	default:freq<=16'd0;
   endcase
end
assign BEEP=beep_reg;
endmodule