分频器+计数器+数码管显示VHDL

天马星空，纯理论写代码，未实操

1.方案一

• 波形（RTL）原理图+代码设计
  
  
  
  
• 代码
  • 1

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
-- 50Mhz
-- 任意Hz分频器
entity divide is
generic
(
	n:integer:=10;				--n分频
	m:integer:=3				--高电平
);
port
(
	clkin:in std_logic; 		--时钟输入		
	clkout: out std_logic	--时钟输出
);
end divide;
-- *************************************************************
architecture fenpin of divide is
signal count:integer range 0 to n-1;		-- 计数值
begin 
	process(clkin)
	begin 
		if(clkin' event and clkin= '1')then
			if(count<n-1) then
				count<=count+1;
			else
				count<=0;
			end if;
		end if;
	end process;
	clkout<='1' when count<m else
		'0';
end fenpin;
		

• 2

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity cnt is
port
(
	clk,clr :in std_logic;
	Q:out integer range 0 to 15
);
end cnt;

architecture counter of cnt is
signal temp: integer range 0 to 15;
begin 
	process(clk,clr)
	begin 
		if(clr='0') then
				temp<=0;
		elsif(clk'event and clk= '1')then
			if temp=9 then 
				temp<=0;
			else 
				temp<=temp+1;
			end if;
		end if;
		Q<=temp;
	end process;
end counter;
		

• 3

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity code47 is
port
(
	in47:in integer range 0 to 15;
	seq:out std_logic_vector(6 downto 0);
	s:out std_logic_vector(3 downto 0)
);
end code47;
-- 共阳管
architecture yima of code47 is

begin
	process(in47)
	begin
		s<="1000";
		case in47 is
			when 0 => seq<="1000000";
			when 1 => seq<="1111001";
			when 2 => seq<="0100100";
			when 3 => seq<="0110000";
			when 4 => seq<="0011001";
			when 5 => seq<="0010010";
			when 6 => seq<="0000010";
			when 7 => seq<="1111000";
			when 8 => seq<="0000000";
			when 9 => seq<="0010000";
			when others => seq<="1111111";
		end case;
			
	end process;
end yima;
				
		

• 4

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity chengxu is
port
(
	clk: in std_logic;
	clr: in std_logic;
	seq:out std_logic_vector(6 downto 0);
	s:out std_logic_vector(3 downto 0)
);
end chengxu;

architecture Dec of chengxu is
component divide 
generic
(
	n:integer;   --n分频
	m:integer	  --高电平
);
port
(
	clkin:in std_logic;
	clkout: out std_logic
);
end component;

component cnt 
port
(
	clk,clr :in std_logic;
	Q:out integer range 0 to 15
);
end component;
component code47 
port
(
	in47:in integer range 0 to 15;
	seq:out std_logic_vector(6 downto 0);
	s:out std_logic_vector(3 downto 0)
);
end component;


signal clkout:std_logic;
signal Qtemp:integer  range 0 to  15;

begin
	U1: divide generic map(10,3)
	port map(clk,clkout);
	U2: cnt port map(clkout,clr,Qtemp);
	U3: code47 port map(Qtemp,seq,s);
end Dec;

2. 方案二

• 波形（RTL）原理图+代码设计
  
  
  
• 代码
• 1

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
-- 50Mhz
-- 任意Hz分频器
entity divide is
generic
(
	n:integer:=4;   			--n分频
	m:integer:=2	  			--高电平
);
port
(
	clkin:in std_logic;		--时钟输入
	clkout: out std_logic	--时钟输出
);
end divide;
-- ****************************************************
architecture fenpin of divide is
signal count:integer range 0 to n-1;    --计数值
begin 
	process(clkin)
	begin 
		if(clkin' event and clkin= '1')then
			if(count<n-1) then
				count<=count+1;
			else
				count<=0;
			end if;
		end if;
	end process;
	clkout<='1' when count<m else
		'0';
end fenpin;
		

• 2

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
-- ****************************************************
-- 任意进制计数器 0-9999
entity cntx is
generic
(	
	num :integer range 0 to 9999:=100	--计数上限
);
port
(
	clk,clr :in std_logic;					--时钟输入，清零
	Q:out integer range 0 to num-1		--计数输出
);
end cntx;
-- ****************************************************
architecture counter of cntx is
signal temp: integer range 0 to num-1;
begin 
	process(clk,clr)
	begin 
		if(clr='0') then
				temp<=0;
		elsif(clk'event and clk= '1')then
			if temp=num-1 then 
				temp<=0;
			else 
				temp<=temp+1;
			end if;
		end if;
		Q<=temp;
	end process;
end counter;
		

• 3

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
-- ****************************************************
-- 四位共阳数码管数值显示
entity codexx is
generic
(
	NumMax:integer range 0 to 9999:=100  --选择计数上限
);
port
(
	incode:in integer range 0 to NumMax-1;  	--数值输入
	clk: in std_logic;							--时钟控制
	seq:out std_logic_vector(6 downto 0);	--段码
	s:out std_logic_vector(3 downto 0)		--位码
);
end codexx;
-- ****************************************************
architecture yima of codexx is

type TT is array(3 downto 0) of integer range 0 to 9;  --自定义数组
signal temp:TT;
signal stemp:std_logic_vector(3 downto 0);
signal biao:integer range 0 to 3:=0;						
begin
	
	temp(0)<=incode rem 10;
	temp(1)<=(incode/10)  rem 10;
	temp(2)<=(incode/100)  rem 10;
	temp(3)<=(incode/1000);
	A:process(clk)				--进程A 检测上升沿，控制显示位
	begin 
		if clk'event and clk='1' then
			if(biao=3) then
				biao<=0;
			else
				biao<=biao+1;
			end if;
		end if;
	end process A;	
	B:process(biao)			--进程B 数值显示
	begin
		stemp <= "0000";
		stemp(biao)<='1';
		case temp(biao) is
			when 0 => seq<="1000000";
			when 1 => seq<="1111001";
			when 2 => seq<="0100100";
			when 3 => seq<="0110000";
			when 4 => seq<="0011001";
			when 5 => seq<="0010010";
			when 6 => seq<="0000010";
			when 7 => seq<="1111000";
			when 8 => seq<="0000000";
			when 9 => seq<="0010000";
			when others => seq<="1111111";
		end case;
		s<=stemp;
	end process B;
	
end yima;
				
		

• 4

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
-- ****************************************************
entity chengxu is
port
(
	clk: in std_logic;					--时钟输入
	clr: in std_logic;					--清零
	seq:out std_logic_vector(6 downto 0);		--段码
	s:out std_logic_vector(3 downto 0)			--位码
);
end chengxu;
-- ****************************************************
architecture Dec of chengxu is
component divide 
generic
(
	n:integer;   --n分频
	m:integer	  --高电平
);
port
(
	clkin:in std_logic;
	clkout: out std_logic
);
end component;
-- ****************************************************
component cntx 
generic
(	
	num :integer 								--计数上限
);
port
(
	clk,clr :in std_logic;					--时钟输入，清零
	Q:out integer range 0 to num-1		--计数输出
);
end component;
-- ****************************************************
component codexx 
generic
(
	NumMax:integer 								--选择计数上限
);
port
(
	incode:in integer range 0 to NumMax-1;  	--数值输入
	clk: in std_logic;							--时钟控制
	seq:out std_logic_vector(6 downto 0);	--段码
	s:out std_logic_vector(3 downto 0)		--位码
);
end component;
-- ****************************************************
signal clkout:std_logic;
signal Qtemp:integer ;
begin
	U1: divide generic map(10,3)
	port map(clk,clkout);
	U2: cntx generic map(10)
	port map(clkout,clr,Qtemp);
	U3: codexx generic map(10)
	port map(Qtemp,clk,seq,s);
end Dec;