imut_du FPGA_作业2

当我对着这个图，根据中间状态A、B、C，E，因为我是严格按照这个图来编程序，为了达到这个图的效果，然后分析，然后列出了表达式和真值表和表达式，

列完写代码

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY w_s IS
PORT (
A_1,A_2,B_1,B_2,D_1: IN STD_LOGIC;
E_OUT: OUT STD_LOGIC
);
END w_s;

ARCHITECTURE ART OF w_s IS
SIGNAL SEL: STD_LOGIC_VECTOR(4 DOWNTO 0); 
BEGIN 
SEL <=A_1&A_2&B_1&B_2&D_1;
WITH SEL SELECT
E_OUT <= A_1 AND A_2 WHEN ("11000" OR"11001"),
         B_1 OR B_2 WHEN ("00101" OR"00100"OR"00011"OR"00111"),
         B_2 AND (NOT D_1) WHEN "00010",
         '0'  WHEN ("00000" OR"00001"),
        ((A_1 AND A_2) OR(B_1 OR B_2)OR ( (NOT D_1) AND B_2)) WHEN OTHERS;
		  
END ART;

编译成功后
Tools---->netlist viewer—>RTL viewer

就能看到和作业一模一样的图拉

提取码：1111
工程连接