七人表决器VHDL代码

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七人表决器VHDL代码

library ieee;
use ieee.std_logic_1164.all;
entity voter7777 is
port( vote:in std_logic_vector(6 downto 0);
pass:out std_logic );
end;
architecture a of voter7777 is
begin
process (vote)
variable cont:integer range 0 to 7;
begin
cont:=0;
for i in 6 downto 0 loop
if vote(i)='1’then
cont:=cont+1;
end if;
end loop;
if cont>3 then
pass<=‘1’;
else
pass<=‘0’;
end if;
end process;
end a;

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