VHDL保留关键字

From VHDL 87：

abs
access
after
alias
all
and
architecture
array
assert
attribute
begin
block
body
buffer
bus
case
component
configuration
constant
disconnect
downto
else
elsif
end
entity
exit
file
for
function
generate
generic
guarded
if
in
inout
is
label
library
linkage
loop
map
mod
nand
new
next
nor
not
null
of
on
open
or
others
out
package
port
procedure
process
range
record
register
rem
report
return
select
severity
signal
subtype
then
to
transport
type
units
until
use
variable
wait
when
while
with
xor

From VHDL 93:

group
impure
inertial
literal
postpones
pure
reject
rol
ror
shared
sla
sll
sra
srl
unaffected
xnor