msp432快速入门第二节之sdk的详解

SDK详解

(一) 目的是快速上手这款单片机,所以一些对于新手不友好的东西我都不会介绍,简略说明就略过。

TI的SDK安装后如此:
在这里插入图片描述(1).metadata没用,似乎是安装后的遗留产品,好让CCS
(2)docs不建议看,入门阶段读datasheet和usermanual就行
(3)example:里边有例子,是重要的文件
(4)kernel :移植RTOS时候会用到的内核文件,入门阶段无用
(5)source:文件包括使用的第三方内核(arm)以及必须使用到的ti的驱动文件,类似stm32的标准库,必须使用;
(6)入门用不到的工具,略过

(二)example文件夹

包括两个文件:
在这里插入图片描述
主要使用裸机的例子,下边的带rtos的略过

nortos文件夹进去后选择板子,我选择第一个,然后出现如此文件目录:
在这里插入图片描述
第一个讲的是demo就是演示模板,大家可以点开第一个把第一个demo的工程下载进去,是一个LED闪烁的demo,注意下载完毕后需要按一下板子正上方的reset按键,之后开始闪烁led,证明你的配置没问题;
第二个是实用驱动的例子,会经常使用这个文件,里边有超多TI的片上设备操作例子;
第三个和后边的用不到,更深入的话需要学习后边几个,现阶段主要使用前俩。

(三)source文件夹

包括第三方的文件,跟移植有关以及TI的驱动库,自己建立工程时必须保留。

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MSP432 低功耗高性能并存10.1 Digital I/O Introduction The digital I/O features include: • Independently programmable individual I/Os • Any combination of input or output • Individually configurable interrupts for ports (available for certain ports only) • Independent input and output data registers • Individually configurable pullup or pulldown resistors • Wake-up capability from ultra-low power modes (available for certain ports only) • Individually configurable high drive I/Os (available for certain I/Os only) Devices within the family may have up to eleven digital I/O ports implemented (P1 to P10 and PJ). Most ports contain eight I/O lines; however, some ports may contain less (see the device-specific data sheet for ports available). Each I/O line is individually configurable for input or output direction, and each can be individually read or written. Each I/O line is individually configurable for pullup or pulldown resistors. Certain ports have interrupt and wake-up capability from ultra-low power modes (see device specific data sheet for ports with interrupt and wake-up capability). Each interrupt can be individually enabled and configured to provide an interrupt on a rising or falling edge of an input signal. All interrupts are fed into an encoded Interrupt Vector register, allowing the application to determine which sub-pin of a port has generated the event. Individual ports can be accessed as byte-wide ports or can be combined into half-word-wide ports. Port pairs P1 and P2, P3 and P4, P5 and P6, P7 and P8, and so on, are associated with the names PA, PB, PC, PD, and so on, respectively. All port registers are handled in this manner with this naming convention. The main exception are the interrupt vector registers, for example, interrupts for ports P1 and P2 must be handled through P1IV and P2IV, PAIV does not exist. When writing to port PA with half-word operations, all 16 bits are written to the port. When writing to the lower byte of port PA using byte operations,

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