VHDL学习：4位/8位全加器

1、4位全加器

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity adder4b is
port(C4: in std_logic;
	  A4: in std_logic_vector(3 downto 0);//输入
	  B4: in std_logic_vector(3 downto 0);//输入
	  S4: out std_logic_vector(3 downto 0);//输出
	  CO4: out std_logic);//进位
end entity adder4b;

architecture ART of adder4b is
	signal S5: std_logic_vector(4 downto 0);
	signal A5,B5: std_logic_vector(4 downto 0);
	begin
		A5 <= '0'& A4;
		B5 <= '0'& B4;
		S5 <= A5 + B5 + C4;
		S4 <= S5(3 downto 0);
		CO4 <= S5(4);
end architecture ART;

仿真图

2、8位全加器

将两个4位全加器组合成一个8位全加器

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity adder88 is 
	port(C8: in std_logic;
		  A8: in std_logic_vector(7 downto 0);
		  B8: in std_logic_vector(7 downto 0);
		  S8: out std_logic_vector(7 downto 0);
		  CO8: out std_logic);
end entity adder88;

architecture ART of adder88 is
	component adder4b is
		port(C4: in std_logic;
			  A4: in std_logic_vector(3 downto 0);
			  B4: in std_logic_vector(3 downto 0);
			  S4: out std_logic_vector(3 downto 0);
			  CO4: out std_logic);
	end component adder4b;//例化4位全加器
signal SC: std_logic;
begin
	U1:adder4b
		port map(C4=>C8, A4=>A8(3 downto 0),B4=>B8(3 downto 0),
					S4=>S8(3 downto 0), CO4=>SC);
	U2:adder4b
		port map(C4=>C8, A4=>A8(7 downto 4),B4=>B8(7 downto 4),
					S4=>S8(7 downto 4), CO4=>CO8);//组合两个4位全加器
end architecture ART;

仿真图

源代码在资源