VHDL学习：两种方式实现四选一选择器

最新推荐文章于 2023-07-20 19:00:34 发布

光阴似水流年

最新推荐文章于 2023-07-20 19:00:34 发布

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方式一

library ieee;
use ieee.std_logic_1164.all;
entity slect1_4 is
	port(S1,S2:in std_logic;
	A,B,C,D:in std_logic;
	Z:out std_logic);
end entity slect1_4;
architecture ART of slect1_4 is
	signal S:std_logic_vector(1 downto 0);
	begin
	S <= S1&S2;
		process(S,A,B,C,D) is
			begin
			case S is
				when "00" => Z <= A;
				when "01" => Z <= B;
				when "10" => Z <= C;
				when "11" => Z <= D;
				when others => Z <= 'X';
			end case;
		end process;
	end architecture ART;

仿真图如下
在这里插入图片描述

方式二

library ieee;
use ieee.std_logic_1164.all;
entity slect1_4s is
	port(S1,S2:in std_logic;
	A,B,C,D:in std_logic;
	Z:out std_logic); 
end entity slect1_4s;
architecture ART of slect1_4s is
signal S:std_logic_vector(1 downto 0);
begin 
S <= S1&S2;
	Z <= A when(S="00") else
		  B when(S="01") else
		  C when(S="10") else
		  D when(S="11") else
		  'X';
end architecture ART;