3-8译码器设计与验证Verilog

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已于 2022-01-22 15:01:40 修改

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分类专栏：小梅哥学习笔记文章标签： fpga开发

于 2022-01-22 15:00:22 首次发布

本文链接：https://blog.csdn.net/qq_44933149/article/details/122637553

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3-8译码器

真值表

a	b	c	out
0	0	0	00000001
0	0	1	00000010
0	1	0	00000100
0	1	1	00001000
1	0	0	00010000
1	0	1	00100000
1	1	0	01000000
1	1	1	10000000

顶层文件

module my3_8(a,b,c,out);

	input a;//输入端口a
	input b;//输入端口b
	input c;//输入端口c
	
	output [7:0] out;//输出端口out
	reg [7:0] out;//output reg [7:0] out;
	
	always@(a,b,c)begin 
		case({a,b,c})
			3'b000:out = 8'b00000001;
			3'b001:out = 8'b00000010;
			3'b010:out = 8'b00000100;
			3'b011:out = 8'b00001000;
			3'b100:out = 8'b00010000;
			3'b101:out = 8'b00100000;
			3'b110:out = 8'b01000000;
			3'b111:out = 8'b10000000;
			//default的使用
		endcase
	end 
endmodule

testbench文件

`timescale 1ns/1ns
module my3_8_tb;
	reg a;
	reg b;
	reg c;

	wire[7:0] out;
	
	my3_8 u1(
	.a(a),
	.b(b),
	.c(c),
	.out(out)
	);
	
	initial begin
		a=0;b=0;c=0;
		#200;
		a=0;b=0;c=1;
		#200;
		a=0;b=1;c=0;
		#200;
		a=0;b=1;c=1;
		#200;
		a=1;b=0;c=0;
		#200;
		a=1;b=0;c=1;
		#200;
		a=1;b=1;c=0;
		#200;
		a=1;b=1;c=1;
		#200;
		$stop;
	
	end
	
endmodule

前仿真

后仿真

未知态

不稳定性

注：由00000001变成00000010会出现两个不稳定状态，即

00000011和00000000

作业：4-16译码器

真值表

a	b	c	d	out
0	0	0	0	0000000000000001
0	0	0	1	0000000000000010
0	0	1	0	0000000000000100
0	0	1	1	0000000000001000
0	1	0	0	0000000000010000
0	1	0	1	0000000000100000
0	1	1	0	0000000001000000
0	1	1	1	0000000010000000
1	0	0	0	0000000100000000
1	0	0	1	0000001000000000
1	0	1	0	0000010000000000
1	0	1	1	0000100000000000
1	1	0	0	0001000000000000
1	1	0	1	0010000000000000
1	1	1	0	0100000000000000
1	1	1	1	1000000000000000

顶层文件
module my4_16(a,b,c,d,out);
	input a;
	input b;
	input c;
	input d;
	
	output [15:0] out;
	
	reg [15:0] out;
	
	always@(a,b,c,d)begin
		case({a,b,c,d})
			4'b0000:out = 16'b0000000000000001;
			4'b0001:out = 16'b0000000000000010;
			4'b0010:out = 16'b0000000000000100;
			4'b0011:out = 16'b0000000000001000;
			4'b0100:out = 16'b0000000000010000;
			4'b0101:out = 16'b0000000000100000;
			4'b0110:out = 16'b0000000001000000;
			4'b0111:out = 16'b0000000010000000;
			4'b1000:out = 16'b0000000100000000;
			4'b1001:out = 16'b0000001000000000;
			4'b1010:out = 16'b0000010000000000;
			4'b1011:out = 16'b0000100000000000;
			4'b1100:out = 16'b0001000000000000;
			4'b1101:out = 16'b0010000000000000;
			4'b1110:out = 16'b0100000000000000;
			4'b1111:out = 16'b1000000000000000;
		endcase
	end
endmodule 


testbench文件
`timescale 1ns/1ns

module my4_16_tb;
	reg a;
	reg b;
	reg c;
	reg d;
	wire [15:0] out;
	
	my4_16 u1(
	.a(a),
	.b(b),
	.c(c),
	.d(d),
	.out(out)
	);
	
	initial begin 
		a=0;b=0;c=0;d=0;
		#200;
		a=0;b=0;c=0;d=1;
		#200;
		a=0;b=0;c=1;d=0;
		#200;
		a=0;b=0;c=1;d=1;
		#200;
		a=0;b=1;c=0;d=0;
		#200;
		a=0;b=1;c=0;d=1;
		#200;
		a=0;b=1;c=1;d=0;
		#200;
		a=0;b=1;c=1;d=1;
		#200;
		a=1;b=0;c=0;d=0;
		#200;
		a=1;b=0;c=0;d=1;
		#200;
		a=1;b=0;c=1;d=0;
		#200;
		a=1;b=0;c=1;d=1;
		#200;
		a=1;b=1;c=0;d=0;
		#200;
		a=1;b=1;c=0;d=1;
		#200;
		a=1;b=1;c=1;d=0;
		#200;
		a=1;b=1;c=1;d=1;
		#200;
		$stop;
	end 
endmodule