1.创建ipcore
2.例化创建的ipcore(将ipcore_inst中copy到顶层文件)
3.将ipcore中的信号端口在顶层文件中说明
module ex_ipcore(
input wire sclk,
output wire oclk1,
output wire oclk2,
output reg [1:0] cnt,
output wire [7:0] odata,
output wire locked
);
reg [7:0] raddr=0;
always @(posedge oclk1) begin
cnt <= cnt + 1'b1;
end
always @ (posedge oclk1) begin
raddr <= raddr + 1'b1;
end
pll1 pll1_inst (
.inclk0 ( sclk ),
.c0 ( oclk1 ),
.c1 ( oclk2 ),
.locked ( locked )
);
rom_8x256 rom_8x256_inst (
.address ( raddr ),
.clock ( oclk1 ),
.q ( odata )
);
endmodule
4.仿真
quit -sim
.main clear
vlib work
vlog ./tb_ex_ipcore.v
vlog ./altera_lib/*.v
vlog ./../design/*.v
vlog ./../ipcore_dir/PLL1/pll1.v
vlog ./../ipcore_dir/rom_8x256.v
vsim -voptargs=+acc work.tb_ex_ipcore
add wave tb_ex_ipcore/ex_ipcore_inst/*
run 1us