MODULSEM VERILOG 串口发送模块

//串口发送模块
`timescale 1ns/10ps
module uart_tx(
	clk,
	res,
	data_in,
	en_data_in,
	TX,
	rdy
	);
	input  clk;
	input  res;
	input[7:0]  data_in;//zhun befasongde shuju
	input  en_data_in;//fasongshinneg
	output TX;
	output rdy;//kogxianbiaozhi 0bioashikongxian

reg[3:0] state;//zhuzhuangtaijijicunqi
reg[9:0] send_buf;//fasong jicunqi
reg[12:0] con;//jisuan botelvzhouqi
reg[9:0] send_flag;//panduanyouyijieshu
reg rdy;
assign TX=send_buf[0];
always@(posedge clk or negedge res)
if(~res) begin
state<=0;send_buf<=1;con<=0;
send_flag<=10'b10_0000_0000;
rdy<=0;
end
else begin
case(state)
//dengdaishinnegxinhao
0:begin if(en_data_in)begin 
send_buf<={1'b1,data_in,1'b0};
send_flag<=10'b10_0000_0000;
rdy<=1;
state<=1;
end
end
//chuankoufasong  jicunqiyouyi
1:begin 
if(con==5000-1)begin 
 con<=0;

 end
 else begin
  con<=con+1;
 end
if(con==5000-1)begin
send_buf[8:0]<=send_buf[9:1];
send_flag[8:0]<=send_flag[9:1];
end

if(send_flag[0]==1)begin
rdy<=0;
state<=0;

end
end

endcase
	end
	endmodule
module uart_tx_tb;
reg clk,res,en_data_in;
reg[7:0]data_in;
wire TX,rdy;
uart_tx uart_tx(  //tongminglihua
	clk,
	res,
	data_in,
	en_data_in,
	TX,
	rdy
	);
initial begin
      clk<=0;res<=0;data_in<=8'h0a;en_data_in<=0;
    #17 res<=1;
    #30  en_data_in<=1;
    #10  en_data_in<=0;
    #1000 $stop;
end
always #5 clk=~clk;



endmodule

结果：