设计一个16位串入并出移位寄存器Design a 16-bit serial-in-parallel-out shift register

module shifter_s1p16(			//串行右移专并行输出
	input clk,
	input reset_n,
	input serial_in,
	output reg [15:0] parallel_out
);
	always@(posedge clk or negedge reset_n)
		if(!reset_n)
			parallel_out <= 0;
		else
			parallel_out <= {serial_in, parallel_out[15:1]};
endmodule