Verilog 数电实验 分频器 很简单的

module fpj_4(clk,sel,c0,c1,c,cnt0,cnt1,x1,x2); //分频3809和13809，占空比20%
input clk,sel;
output reg c0=0;
output reg c1=0;
output reg c=0;
output reg x1=0;
output reg x2=0;
output reg [16:0]cnt0=17'b0;
output reg [12:0]cnt1=13'b1;

always@(posedge clk)

begin
case(x1)
0:
begin
if(cnt0==17'd10500)   //  50000000/3809/2=6563,0.8*13126=10500
	begin
	cnt0<=0;
	c0<=~c0;
	x1=~x1;
	end
else
	begin
	cnt0<=cnt0+1'b1;
	end
end
1:
begin
if(cnt0==17'd2625)   //  50000000/3809/2=6563,0.2*13126=2625
	begin
	cnt0<=0;
	c0<=~c0;
	x1=~x1;
	end
else
	begin
	cnt0<=cnt0+1'b1;
	end
end
default: ;
endcase
end


always@(posedge clk)
begin
case(x2)
0:
begin
if(cnt1==13'd2897)   //  50000000/13809=3621,0.8*3621=2897
	begin
	cnt1<=0;
	c1<=~c1;
	x2=~x2;
	end
else
	begin
	cnt1<=cnt1+1'b1;
	end
end
1:
begin
if(cnt1==13'd724)   //  0.2*3621=724
	begin
	cnt1<=0;
	c1<=~c1;
	x2=~x2;
	end
else
	begin
	cnt1<=cnt1+1'b1;
	end
end
default: ;
endcase
end

always@(posedge clk)
begin
	if(sel==0)
	c<=c0;
	else c<=c1;
end
endmodule

 有参考 @我叫辰辰啦的 代码