verilog 数电实验 占空比测量仪 自己写的不是很好

module lab_7(clk,ft,rst_n,c0,out,led,d0,d1,d2,d3,BITS,DIGS);
input clk;
input ft;
input rst_n;//拨1测量周期，拨0测量占空比
output c0;
output led;
reg [15:0]T;//测量周期
reg [15:0]T2;//测量高电平时间
output [15:0]out;
wire ft_state_rise,ft_rise,ft_down;//ft_state上升沿检测，ft下降沿检测
reg [15:0]cout;//计数器，测量周期
reg [15:0]cout2;//计数器2,测量占空比
reg ft_state,n_ft_state,o_ft_state,n_ft,o_ft;
output wire[7:0] BITS;
output wire[7:0]DIGS;
output wire[3:0] d3,d2,d1,d0;

PLL_Test pll1(clk,c0);

always @(posedge ft)begin
  ft_state<=~ft_state;//一个周期变化一次
end

always @(posedge c0)begin
  n_ft_state<=ft_state;
  o_ft_state<=n_ft_state;//由于非阻塞式，在结束后才会变化，o_f0为f0的上一个状态
  n_ft<=ft;
  o_ft<=n_ft;//o_ft为ft的上一个状态
 end
 assign ft_state_rise=n_ft_state&(~o_ft_state);//检测state的上升沿变化
 assign ft_rise=n_ft&(~o_ft);//检测ft的上升沿变化
 assign ft_down=(~n_ft)&o_ft;//检测ft的下降沿变化

always @(posedge c0)begin
if(ft_state_rise)begin 
T<=5*cout;
cout<=1;
end
else begin cout<=cout+1'b1;end
if(ft_rise)begin
cout2<=1;
end
else if(ft_down)begin
T2<=10*cout2;
end
else begin cout2<=cout2+1'b1;end

end

assign out=(rst_n?T:(10000*T2/T));//rst_n=1时，out=T,rst_n=0时，out=占空比
assign led=(T>10000||T<500?1:0);//超量程时LED亮

//code(c0,d0,d1,d2,d3,BITS,DIGS)

assign d3=out%10;// 个
assign d2=out/10%10;//十
assign d1=out/100%10;//百
assign d0=out/1000%10;//千

lab_7_1 my_code(clk,rst_n,d0,d1,d2,d3,BITS,DIGS);

endmodule

module lab_7_1(c0,rst_n,d0,d1,d2,d3,BITS,DIGS);
input c0,rst_n;
input [7:0] d0,d1,d2,d3;//高位到低位
reg [1:0] sel=0;//选择00 01 10 11
reg [17:0] cnt0;
reg seg_clock;
output reg[7:0] BITS;
output reg[7:0]DIGS;


always@(posedge c0)
begin
if(cnt0 >= 17'd50000)   //  
	begin
	cnt0<=0;
	end
else if(cnt0 > 17'd25000)
	begin
	seg_clock<=0;
	cnt0<=cnt0+1'b1;
	end
else if(cnt0 <= 17'd25000)
	begin
	cnt0<=cnt0+1'b1;
	seg_clock<=1;
	end
end

always@(posedge seg_clock)
begin
	if(sel==2'b00)
	begin
	DIGS=8'b10000000;
	case(d0)
	4'd0: BITS <=8'b11111100;
	4'd1: BITS <=8'b01100000;
	4'd2: BITS <=8'b11011010;
	4'd3: BITS <=8'b11110010;
	4'd4: BITS <=8'b01100110;
	4'd5: BITS <=8'b10110110;
	4'd6: BITS <=8'b10111110;
	4'd7: BITS <=8'b11100000;
	4'd8: BITS <=8'b11111110;
	4'd9: BITS <=8'b11110110;
	default:BITS<=8'b0000000;
	endcase
	end
	
	else if(sel==2'b01)
	begin
	DIGS=8'b01000000;
	if(rst_n==1)
	begin
	case(d1)
	4'd0: BITS <=8'b11111100;
	4'd1: BITS <=8'b01100000;
	4'd2: BITS <=8'b11011010;
	4'd3: BITS <=8'b11110010;
	4'd4: BITS <=8'b01100110;
	4'd5: BITS <=8'b10110110;
	4'd6: BITS <=8'b10111110;
	4'd7: BITS <=8'b11100000;
	4'd8: BITS <=8'b11111110;
	4'd9: BITS <=8'b11110110;
	default:BITS<=8'b0000000;
	endcase
	end
	else
	begin
	case(d1)
	4'd0: BITS <=8'b11111101;
	4'd1: BITS <=8'b01100001;
	4'd2: BITS <=8'b11011011;
	4'd3: BITS <=8'b11110011;
	4'd4: BITS <=8'b01100111;
	4'd5: BITS <=8'b10110111;
	4'd6: BITS <=8'b10111111;
	4'd7: BITS <=8'b11100001;
	4'd8: BITS <=8'b11111111;
	4'd9: BITS <=8'b11110111;
	default:BITS<=8'b00000000;
	endcase
	end
	end
	else if(sel==2'b10)
	begin
	DIGS=8'b00100000;
	case(d2)
	4'd0: BITS <=8'b11111100;
	4'd1: BITS <=8'b01100000;
	4'd2: BITS <=8'b11011010;
	4'd3: BITS <=8'b11110010;
	4'd4: BITS <=8'b01100110;
	4'd5: BITS <=8'b10110110;
	4'd6: BITS <=8'b10111110;
	4'd7: BITS <=8'b11100000;
	4'd8: BITS <=8'b11111110;
	4'd9: BITS <=8'b11110110;
	default:BITS<=8'b0000000;
	endcase
	end
	
	else 
	begin
	   DIGS=8'b00010000;
	case(d3)
	4'd0: BITS <=8'b11111100;
	4'd1: BITS <=8'b01100000;
	4'd2: BITS <=8'b11011010;
	4'd3: BITS <=8'b11110010;
	4'd4: BITS <=8'b01100110;
	4'd5: BITS <=8'b10110110;
	4'd6: BITS <=8'b10111110;
	4'd7: BITS <=8'b11100000;
	4'd8: BITS <=8'b11111110;
	4'd9: BITS <=8'b11110110;
	default:BITS<=8'b0000000;
	endcase
	end
	sel<=sel+1;
end
endmodule

  用到了PLL

 PLL_Test	PLL_Test_inst (
	.inclk0 ( inclk0_sig ),
	.c0 ( c0_sig )
	);