FPGA学习verilog实现P = (A+B)*(C-D)

层次化设计

设计目标：实现P = (A+B)*(C-D)

框图

代码

顶层模块

module TEST1_TOP (
    input wire [7:0]A,
    input wire [7:0]B,
    input wire [7:0]C,
    input wire [7:0]D,
    output wire [17:0]P
);

wire [8:0]add_result;
wire [8:0]sub_result;  //声明中间变量

ADD ADD_1(
    .A(A),
    .B(B),
    .add_result(add_result)
);

SUB SUB_1(
    .A(C),
    .B(D),
    .sub_result(sub_result)
);

MULT MULT_1(
    .E(add_result),
    .F(sub_result),
    .P(P)
);
endmodule

ADD模块

module ADD (
    input wire [7:0]A,
    input wire [7:0]B,

    output wire [8:0] add_result
);
    
assign add_result = A + B;

endmodule

SUB模块

module SUB (
    input wire [7:0]A,
    input wire [7:0]B,

    output wire [8:0] sub_result
);
    
assign sub_result = A - B;

endmodule

MULT模块

module MULT (
    input wire [8:0]E,
    input wire [8:0]F,

    output wire [17:0] P
);
    
assign P = E * F;

endmodule

tb文件

`timescale 1ns/1ps

module TEST1_TOP_tb ();
    
reg [7:0]A;
reg [7:0]B;
reg [7:0]C;
reg [7:0]D;
wire [17:0]P;

initial begin
    A = 8'd0;
    B = 8'd0;
    C = 8'd0;
    D = 8'd0;
end

always #10 A = {$random} % 256;
always #10 B = {$random} % 256;
always #10 C = {$random} % 256;
always #10 D = {$random} % 256;

TEST1_TOP TEST1_TOP_1(
    .A(A),
    .B(B),
    .C(C),
    .D(D),
    .P(P)
);

endmodule

仿真结果

目前不考虑无法计算的项目，如12/0，仅作设计流程学习。