FPGA学习verilog编写D触发器

时序逻辑学习

设计目标：实现D触发器

框图

代码

D_FF.v代码

module D_FF (
    input wire clk,
    input wire rst_n,
    input wire D,
    output reg  Q,
    output wire Q_NOT_GATE
);

always @(posedge clk or negedge rst_n) begin
    if(~rst_n)
            Q <= 1'b0;
        else
            Q <= D;  
end
assign Q_NOT_GATE = ~Q;

endmodule

tb文件

`timescale 1ns/1ps

module D_FF_tb ();
    
reg clk;
reg rst_n;
reg D;
wire Q;
wire Q_NOT_GATE;

initial begin
    clk = 1'b0;
    rst_n = 1'b0;
    D = 1'b0;
    #5
    rst_n = 1'b1;
end


//50Mhz  20ns
always #10 clk = ~clk;
always #20.1 D = {$random} % 2;

D_FF D_FF_1(
    .clk(clk),
    .rst_n(rst_n),
    .D(D),
    .Q(Q),
    .Q_NOT_GATE(Q_NOT_GATE)
);

endmodule

仿真结果