前言
本文是FPGA学习的第三篇,通过本次实验,我们将会对VGA有一个初步的认识,至于更深远的学习可以根据需要学习,比如可以制作VGA游戏等。
一、什么是VGA?
VGA(Video Graphics Array)还有一个名称叫D-Sub。是模拟信号,只能传输视频信号,VGA接口共有15针,分成3排,每排5个孔,是显卡上应用最为广泛的接口类型,绝大多数显卡都带有此种接口。它传输红、绿、蓝模拟信号以及同步信号(水平和垂直信号)。使用VGA连接设备,线缆长度最好不要超过10米,而且要注意接头是否安装牢固,否则可能引起图像中出现虚影,另外VGA只能传输VGA支持在640×480的较高分辨率下同时显示16种色彩或256种灰度,同时在320×240分辨率下可以同时显示256种颜色。
特点:
1、是模拟信号的传输,随着显示器的分辨率越高画面就会越模糊。一般模拟信号在超过1280×1024分辨率以上的情况下就会出现明显的误差。
2、因为是模拟信息,信号极其容易受干扰。
3、不能传达音频。
4、一般不加放大器和转换器在30米左右,加放大器和放大转换器可以到150米。
VGA显示原理
数字信号描述的信号是由一个个点组成的,在信号的变化中是不连贯的,而模拟信号的变化是一个连续的曲线,所以模拟信号的给人的真实感更好。当数字信号转换至模拟信号的时候,直接出来的也是一个个的点(数字信号的采样点),而没有描述的部分会由转换程序自动生成(类似与3D的抗锯齿技术)以形成连续的模拟信号波形。模拟信号转换至数字信号的时候,连续的模拟信号转换为描述一个个点的数字信号,信号变得不完整。从这个过程看,数字信号转换为模拟信号是有增强而不是有损失,而模拟信号转换到数字信号才会有损失。
而在VGA传输过程中,VGA转LVDS驱动液晶面板的信号损失可以忽略,因为在前后端数字采样率相同的情况下,这些损失的信号本来就是(将数字信号转换为模拟信号的时候)程序自动填补的部分,不是数字信号源原本信号的损失。如图:
管脚定义:
管脚 | 定义 |
---|---|
1 | 红基色 |
2 | 绿基色 |
3 | 蓝基色 |
4 | 地址码 ID Bit |
5 | 自测试 |
6 | 红地 |
7 | 绿地 |
8 | 蓝地 |
9 | 保留(各家定义不同) |
10 | 数字码 |
11 | 地址码 |
12 | 地址码 |
13 | 行同步 |
14 | 场同步 |
15 | 地址码(各家定义不同) |
VGA通信协议:
时序要求
从VGA的时序图中, 可以看出,帧时序和行时序都产生了四部分,帧时序的四个部分分别是:同步脉冲(o),显示后沿(p),显示时序段(q)和显示前沿(r)。其中同步脉冲(o),显示后沿(p)和显示前沿(r)是消隐区,RGB信号无效,屏幕不显示数据。显示数据段(q)是有效数据区。行时序的四个部分是:同步脉冲(a),显示后沿(b),显示时序段(c)和显示前沿(d)。其中同步脉冲(a),显示后沿(b),显示前沿(d)是消隐区,RGB信号无效,屏幕不显示数据。显示时序段(c)是有效数据区。
VGA常用刷新率时序表
二、VGA显示字符测试
VGA 显示字符的原理是将文本编码转换成数字信号,并通过VGA 显示适配器发送到显示器上。
具体来说,VGA 显示器使用了一种称为“字符发生器”的电路,它将每个字符的图案编码存储在内存中。这些编码被称为“字符集”,它们由8个二进制位组成,可以表示256个不同的字符,包括字母、数字和符号等。每个字符在显示器屏幕上都有一个对应的像素矩阵。
当计算机向显示器发送文本信息时,计算机将每个字符的字符集编码发送到显示适配器。显示适配器使用这些编码来选择正确的字符图案,并将其转换为一系列像素信号,将它们发送到显示器上。显示器将这些像素信号解码并显示在屏幕上,从而呈现出文本信息。
所以这里我们将会用到汉字取模工具:链接:https://pan.baidu.com/s/1EInMlOq8J4y0kcXMPFYUGQ
提取码:1234
字模数据:
{0x00,0x00,0x00,0x1F,0x12,0x12,0x12,0x12,0x12,0x12,0x10,0x10,0x10,0x10,0x10,0x31},
{0x11,0x00,0x00,0x00,0x00,0x00,0x0C,0x08,0x10,0x1F,0xF0,0x28,0x28,0x49,0xFE,0x88},
{0x88,0x89,0x88,0x88,0x18,0x08,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},
{0x00,0x00,0x00,0x00,0x00,0x80,0xC0,0x40,0x00,0x00,0x00,0x00},/*"陈",0*/
{0x00,0x00,0x00,0x0C,0x04,0x00,0x20,0x18,0x08,0x04,0x0B,0x08,0x11,0x13,0x32,0x10},
{0x00,0x00,0x00,0x00,0x00,0x20,0x30,0x23,0x5C,0x80,0x06,0x7B,0x52,0x52,0xFF,0xA2},
{0x12,0xFF,0x05,0x04,0x2C,0x18,0x08,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},
{0x00,0x00,0xE0,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00},/*"海",1*/
{0x00,0x06,0x02,0x02,0x1F,0x02,0x0F,0x02,0x7D,0x01,0x0F,0x0F,0x09,0x0F,0x11,0x11},
{0x13,0x00,0x00,0x00,0x00,0x08,0x08,0x93,0x1E,0x24,0x45,0xBB,0x08,0x1F,0x25,0x05},
{0x3E,0x04,0x04,0x04,0x0C,0x18,0x08,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80},
{0x80,0xE0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"静",2*/
{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0x00,0x00,0x00,0x00,0x00,0x00},
{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0x00,0x00},
{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},
{0x00,0xF0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"—",3*/
{0x00,0x00,0x00,0x06,0x04,0x0C,0x18,0x10,0x3F,0x73,0x61,0x60,0x40,0x60,0x61,0x3F},
{0x1E,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x80,0x80},
{0x80,0x80,0x80,0x00,0x00,0x00,0x00,0x00},/*"6",4*/
{0x00,0x00,0x00,0x1E,0x33,0x61,0x41,0x01,0x03,0x0E,0x03,0x01,0x01,0x41,0x61,0x3F},
{0x1C,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x80,0x00,0x00,0x00,0x00,0x80},
{0x80,0x80,0x00,0x00,0x00,0x00,0x00,0x00},/*"3",5*/
{0x00,0x00,0x00,0x1E,0x3F,0x61,0x41,0x01,0x03,0x03,0x06,0x0C,0x08,0x18,0x30,0x7F},
{0x7F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x80,0x80,0x00,0x00,0x00,0x00},
{0x00,0x00,0x00,0x80,0x80,0x00,0x00,0x00},/*"2",6*/
{0x00,0x00,0x00,0x1E,0x3F,0x61,0x61,0x61,0x41,0x41,0x41,0x41,0x61,0x61,0x23,0x3F},
{0x0C,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x80,0x80,0x80,0x80,0x80},
{0x80,0x80,0x00,0x00,0x00,0x00,0x00,0x00},/*"0",7*/
{0x00,0x00,0x00,0x1E,0x3F,0x61,0x61,0x61,0x41,0x41,0x41,0x41,0x61,0x61,0x23,0x3F},
{0x0C,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x80,0x80,0x80,0x80,0x80},
{0x80,0x80,0x00,0x00,0x00,0x00,0x00,0x00},/*"0",8*/
{0x00,0x00,0x00,0x7F,0x7F,0x01,0x01,0x03,0x02,0x06,0x04,0x0C,0x08,0x08,0x18,0x18},
{0x10,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x80,0x80,0x00,0x00,0x00,0x00,0x00,0x00},
{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"7",9*/
{0x00,0x00,0x00,0x1E,0x3F,0x61,0x61,0x61,0x41,0x41,0x41,0x41,0x61,0x61,0x23,0x3F},
{0x0C,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x80,0x80,0x80,0x80,0x80},
{0x80,0x80,0x00,0x00,0x00,0x00,0x00,0x00},/*"0",10*/
{0x00,0x00,0x00,0x06,0x04,0x0C,0x18,0x10,0x3F,0x73,0x61,0x60,0x40,0x60,0x61,0x3F},
{0x1E,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x80,0x80},
{0x80,0x80,0x80,0x00,0x00,0x00,0x00,0x00},/*"6",11*/
{0x00,0x00,0x00,0x1E,0x3F,0x61,0x61,0x61,0x41,0x41,0x41,0x41,0x61,0x61,0x23,0x3F},
{0x0C,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x80,0x80,0x80,0x80,0x80},
{0x80,0x80,0x00,0x00,0x00,0x00,0x00,0x00},/*"0",12*/
{0x00,0x00,0x00,0x04,0x0C,0x1C,0x3C,0x0C,0x0C,0x0C,0x0C,0x0C,0x0C,0x0C,0x0C,0x0C},
{0x0C,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},
{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"1",13*/
{0x00,0x00,0x00,0x1E,0x33,0x61,0x41,0x01,0x03,0x0E,0x03,0x01,0x01,0x41,0x61,0x3F},
{0x1C,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x80,0x00,0x00,0x00,0x00,0x80},
{0x80,0x80,0x00,0x00,0x00,0x00,0x00,0x00},/*"3",14*/
{0x00,0x00,0x00,0x1E,0x3F,0x61,0x61,0x61,0x41,0x41,0x41,0x41,0x61,0x61,0x23,0x3F},
{0x0C,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x80,0x80,0x80,0x80,0x80},
{0x80,0x80,0x00,0x00,0x00,0x00,0x00,0x00},/*"0",15*/
说明:
这里使用点阵显示时,汉字是1616点阵,而符号或是数字或是英文字母是3216点阵。
点阵拼接时,用第一个字的前4位拼上下一个字的前4位…一直到最后一个字,它们构成VGA显示的一行。
代码实现:
module VGA_test(
OSC_50, //原CLK2_50时钟信号
VGA_CLK, //VGA自时钟
VGA_HS, //行同步信号
VGA_VS, //场同步信号
VGA_BLANK, //复合空白信号控制信号 当BLANK为低电平时模拟视频输出消隐电平,此时从R9~R0,G9~G0,B9~B0输入的所有数据被忽略
VGA_SYNC, //符合同步控制信号 行时序和场时序都要产生同步脉冲
VGA_R, //VGA绿色
VGA_B, //VGA蓝色
VGA_G); //VGA绿色
input OSC_50; //外部时钟信号CLK2_50
output VGA_CLK,VGA_HS,VGA_VS,VGA_BLANK,VGA_SYNC;
output [7:0] VGA_R,VGA_B,VGA_G;
parameter H_FRONT = 16; //行同步前沿信号周期长
parameter H_SYNC = 96; //行同步信号周期长
parameter H_BACK = 48; //行同步后沿信号周期长
parameter H_ACT = 640; //行显示周期长
parameter H_BLANK = H_FRONT+H_SYNC+H_BACK; //行空白信号总周期长
parameter H_TOTAL = H_FRONT+H_SYNC+H_BACK+H_ACT; //行总周期长耗时
parameter V_FRONT = 11; //场同步前沿信号周期长
parameter V_SYNC = 2; //场同步信号周期长
parameter V_BACK = 31; //场同步后沿信号周期长
parameter V_ACT = 480; //场显示周期长
parameter V_BLANK = V_FRONT+V_SYNC+V_BACK; //场空白信号总周期长
parameter V_TOTAL = V_FRONT+V_SYNC+V_BACK+V_ACT; //场总周期长耗时
reg [10:0] H_Cont; //行周期计数器
reg [10:0] V_Cont; //场周期计数器
wire [7:0] VGA_R; //VGA红色控制线
wire [7:0] VGA_G; //VGA绿色控制线
wire [7:0] VGA_B; //VGA蓝色控制线
reg VGA_HS;
reg VGA_VS;
reg [10:0] X; //当前行第几个像素点
reg [10:0] Y; //当前场第几行
reg CLK_25;
always@(posedge OSC_50)
begin
CLK_25=~CLK_25; //时钟
end
assign VGA_SYNC = 1'b0; //同步信号低电平
assign VGA_BLANK = ~((H_Cont<H_BLANK)||(V_Cont<V_BLANK)); //当行计数器小于行空白总长或场计数器小于场空白总长时,空白信号低电平
assign VGA_CLK = ~CLK_to_DAC; //VGA时钟等于CLK_25取反
assign CLK_to_DAC = CLK_25;
always@(posedge CLK_to_DAC)
begin
if(H_Cont<H_TOTAL) //如果行计数器小于行总时长
H_Cont<=H_Cont+1'b1; //行计数器+1
else H_Cont<=0; //否则行计数器清零
if(H_Cont==H_FRONT-1) //如果行计数器等于行前沿空白时间-1
VGA_HS<=1'b0; //行同步信号置0
if(H_Cont==H_FRONT+H_SYNC-1) //如果行计数器等于行前沿+行同步-1
VGA_HS<=1'b1; //行同步信号置1
if(H_Cont>=H_BLANK) //如果行计数器大于等于行空白总时长
X<=H_Cont-H_BLANK; //X等于行计数器-行空白总时长 (X为当前行第几个像素点)
else X<=0; //否则X为0
end
always@(posedge VGA_HS)
begin
if(V_Cont<V_TOTAL) //如果场计数器小于行总时长
V_Cont<=V_Cont+1'b1; //场计数器+1
else V_Cont<=0; //否则场计数器清零
if(V_Cont==V_FRONT-1) //如果场计数器等于场前沿空白时间-1
VGA_VS<=1'b0; //场同步信号置0
if(V_Cont==V_FRONT+V_SYNC-1) //如果场计数器等于行前沿+场同步-1
VGA_VS<=1'b1; //场同步信号置1
if(V_Cont>=V_BLANK) //如果场计数器大于等于场空白总时长
Y<=V_Cont-V_BLANK; //Y等于场计数器-场空白总时长 (Y为当前场第几行)
else Y<=0; //否则Y为0
end
reg valid_yr;
always@(posedge CLK_to_DAC)
if(V_Cont == 10'd32) //场计数器=32时
valid_yr<=1'b1; //行输入激活
else if(V_Cont==10'd512) //场计数器=512时
valid_yr<=1'b0; //行输入冻结
wire valid_y=valid_yr; //连线
reg valid_r;
always@(posedge CLK_to_DAC)
if((H_Cont == 10'd32)&&valid_y) //行计数器=32时
valid_r<=1'b1; //像素输入激活
else if((H_Cont==10'd512)&&valid_y) //行计数器=512时
valid_r<=1'b0; //像素输入冻结
wire valid = valid_r; //连线
wire[10:0] x_dis; //像素显示控制信号
wire[10:0] y_dis; //行显示控制信号
assign x_dis=X; //连线X
assign y_dis=Y; //连线Y
parameter
char_line00=240'h0040010010400000000000000000000000000000000000000000000000000000,
char_line01=240'h7840210010400000000000000000000000000000000000000000000000000000,
char_line02=240'h484011fcfe780000000000000000000000000000000000000000000000000000,
char_line03=240'h57fe12001088000018003c003c00180018007e0018001800180008003c001800,
char_line04=240'h508085f87c100000240042004200240024004200240024002400380042002400,
char_line05=240'h6120410811fc0000400042004200420042000400420040004200080042004200,
char_line06=240'h51204948fe240000400002004200420042000400420040004200080002004200,
char_line07=240'h4a20092800247ffc5c000400020042004200080042005c004200080004004200,
char_line08=240'h4bfc17fe7dfe0000620018000400420042000800420062004200080018004200,
char_line09=240'h4820110844240000420004000800420042001000420042004200080004004200,
char_line0a=240'h6928e2487c240000420002001000420042001000420042004200080002004200,
char_line0b=240'h5124222845fc0000420042002000420042001000420042004200080042004200,
char_line0c=240'h422223fc7c240000220042004200240024001000240022002400080042002400,
char_line0d=240'h44222008442000001c003c007e0018001800100018001c0018003e003c001800,
char_line0e=240'h40a0205054a00000000000000000000000000000000000000000000000000000,
char_line0f=240'h4040002048400000000000000000000000000000000000000000000000000000;
reg[7:0] char_bit;
always@(posedge CLK_to_DAC)
if(X==10'd180)char_bit<=9'd240; //当显示到144像素时准备开始输出图像数据
else if(X>10'd180&&X<10'd420) //左边距屏幕144像素到416像素时 416=144+272(图像宽度)
char_bit<=char_bit-1'b1; //倒着输出图像信息
reg[29:0] vga_rgb; //定义颜色缓存
always@(posedge CLK_to_DAC)
if(X>10'd180&&X<10'd420) //X控制图像的横向显示边界:左边距屏幕左边144像素 右边界距屏幕左边界416像素
begin case(Y) //Y控制图像的纵向显示边界:从距离屏幕顶部160像素开始显示第一行数据
10'd200:
if(char_line00[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000; //如果该行有数据 则颜色为红色
else vga_rgb<=30'b0000000000_0000000000_0000000000; //否则为黑色
10'd201:
if(char_line01[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd202:
if(char_line02[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd203:
if(char_line03[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd204:
if(char_line04[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd205:
if(char_line05[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd206:
if(char_line06[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd207:
if(char_line07[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd208:
if(char_line08[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd209:
if(char_line09[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd210:
if(char_line0a[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd211:
if(char_line0b[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd212:
if(char_line0c[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd213:
if(char_line0d[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd214:
if(char_line0e[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd215:
if(char_line0f[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
default:vga_rgb<=30'h0000000000; //默认颜色黑色
endcase
end
else vga_rgb<=30'h000000000; //否则黑色
assign VGA_R=vga_rgb[23:16];
assign VGA_G=vga_rgb[15:8];
assign VGA_B=vga_rgb[7:0];
endmodule
显示效果:
三、VGA显示彩色条纹
代码实现
module VGA_colorbar_test(
OSC_50, //原CLK2_50时钟信号
VGA_CLK, //VGA自时钟
VGA_HS, //行同步信号
VGA_VS, //场同步信号
VGA_BLANK, //复合空白信号控制信号 当BLANK为低电平时模拟视频输出消隐电平,此时从R9~R0,G9~G0,B9~B0输入的所有数据被忽略
VGA_SYNC, //符合同步控制信号 行时序和场时序都要产生同步脉冲
VGA_R, //VGA绿色
VGA_B, //VGA蓝色
VGA_G); //VGA绿色
input OSC_50; //外部时钟信号CLK2_50
output VGA_CLK,VGA_HS,VGA_VS,VGA_BLANK,VGA_SYNC;
output [7:0] VGA_R,VGA_B,VGA_G;
parameter H_FRONT = 16; //行同步前沿信号周期长
parameter H_SYNC = 96; //行同步信号周期长
parameter H_BACK = 48; //行同步后沿信号周期长
parameter H_ACT = 640; //行显示周期长
parameter H_BLANK = H_FRONT+H_SYNC+H_BACK; //行空白信号总周期长
parameter H_TOTAL = H_FRONT+H_SYNC+H_BACK+H_ACT; //行总周期长耗时
parameter V_FRONT = 11; //场同步前沿信号周期长
parameter V_SYNC = 2; //场同步信号周期长
parameter V_BACK = 31; //场同步后沿信号周期长
parameter V_ACT = 480; //场显示周期长
parameter V_BLANK = V_FRONT+V_SYNC+V_BACK; //场空白信号总周期长
parameter V_TOTAL = V_FRONT+V_SYNC+V_BACK+V_ACT; //场总周期长耗时
reg [10:0] H_Cont; //行周期计数器
reg [10:0] V_Cont; //场周期计数器
wire [7:0] VGA_R; //VGA红色控制线
wire [7:0] VGA_G; //VGA绿色控制线
wire [7:0] VGA_B; //VGA蓝色控制线
reg VGA_HS;
reg VGA_VS;
reg [10:0] X; //当前行第几个像素点
reg [10:0] Y; //当前场第几行
reg CLK_25;
always@(posedge OSC_50)begin
CLK_25=~CLK_25; //时钟
end
assign VGA_SYNC = 1'b0; //同步信号低电平
assign VGA_BLANK = ~((H_Cont<H_BLANK)||(V_Cont<V_BLANK)); //当行计数器小于行空白总长或场计数器小于场空白总长时,空白信号低电平
assign VGA_CLK = ~CLK_to_DAC; //VGA时钟等于CLK_25取反
assign CLK_to_DAC = CLK_25;
always@(posedge CLK_to_DAC)begin
if(H_Cont<H_TOTAL) //如果行计数器小于行总时长
H_Cont<=H_Cont+1'b1; //行计数器+1
else H_Cont<=0; //否则行计数器清零
if(H_Cont==H_FRONT-1) //如果行计数器等于行前沿空白时间-1
VGA_HS<=1'b0; //行同步信号置0
if(H_Cont==H_FRONT+H_SYNC-1) //如果行计数器等于行前沿+行同步-1
VGA_HS<=1'b1; //行同步信号置1
if(H_Cont>=H_BLANK) //如果行计数器大于等于行空白总时长
X<=H_Cont-H_BLANK; //X等于行计数器-行空白总时长 (X为当前行第几个像素点)
else X<=0; //否则X为0
end
always@(posedge VGA_HS)begin
if(V_Cont<V_TOTAL) //如果场计数器小于行总时长
V_Cont<=V_Cont+1'b1; //场计数器+1
else V_Cont<=0; //否则场计数器清零
if(V_Cont==V_FRONT-1) //如果场计数器等于场前沿空白时间-1
VGA_VS<=1'b0; //场同步信号置0
if(V_Cont==V_FRONT+V_SYNC-1) //如果场计数器等于行前沿+场同步-1
VGA_VS<=1'b1; //场同步信号置1
if(V_Cont>=V_BLANK) //如果场计数器大于等于场空白总时长
Y<=V_Cont-V_BLANK; //Y等于场计数器-场空白总时长 (Y为当前场第几行)
else Y<=0; //否则Y为0
end
reg valid_yr;
always@(posedge CLK_to_DAC)begin
if(V_Cont == 10'd32) //场计数器=32时
valid_yr<=1'b1; //行输入激活
else if(V_Cont==10'd512) //场计数器=512时
valid_yr<=1'b0; //行输入冻结
end
wire valid_y=valid_yr; //连线
reg valid_r;
always@(posedge CLK_to_DAC)begin
if((H_Cont == 10'd32)&&valid_y) //行计数器=32时
valid_r<=1'b1; //像素输入激活
else if((H_Cont==10'd512)&&valid_y) //行计数器=512时
valid_r<=1'b0; //像素输入冻结
end
wire valid = valid_r; //连线
assign x_dis=X; //连线X
assign y_dis=Y; //连线Y
// reg[7:0] char_bit;
// always@(posedge CLK_to_DAC)
// if(X==10'd144)char_bit<=9'd240; //当显示到144像素时准备开始输出图像数据
// else if(X>10'd144&&X<10'd384) //左边距屏幕144像素到416像素时 416=144+272(图像宽度)
// char_bit<=char_bit-1'b1; //倒着输出图像信息
reg[29:0] vga_rgb; //定义颜色缓存
always@(posedge CLK_to_DAC) begin
if(X>=0&&X<200)begin //X控制图像的横向显示边界:左边距屏幕左边144像素 右边界距屏幕左边界416像素
vga_rgb<=30'hffffffffff; //白色
end
else if(X>=200&&X<400)begin
vga_rgb<=30'hf00ff65f1f;
end
else if(X>=400&&X<600)begin
vga_rgb<=30'h9563486251;
end
else begin
vga_rgb<=30'h5864928654;
end
end
assign VGA_R=vga_rgb[23:16];
assign VGA_G=vga_rgb[15:8];
assign VGA_B=vga_rgb[7:0];
endmodule
显示效果
四、VGA显示彩色图片
该部分使用了EP4CE6F17C8
在前面的学习中了解到图像的格式有多种,例如JPEG,BMP,PNG,JPG等,图像的位数也有单色、16色、256色、4096色、16位真彩色、24位真彩色、32位真彩色在这里插入图片描述
这几种。
VGA的驱动程序显示的格式为RGB565,我们先找到一张需要显示的彩色图片,经过处理,将该图片转化为ROM可以存储的格式,然后VGA驱动程序从ROM中读取数据,输出到VGA显示屏显示。尽量选一张小的图片,因为ROM存储空间有限。
使用BMP2Mif软件将bmp格式图片转换为hex文件
新建Quartus工程,产生ROM IP核,将生成的mif文件保存在ROM中
双击选择ROM:1-PORT
取消勾选q
加载HEX文件
同时还需要用到PLL的IP核调用,可以参考https://blog.csdn.net/qq_45659777/article/details/124955399
生成一个25MHZ的时钟。
从ROM取出图片数据
module data_drive (
input wire vga_clk,
input wire rst_n,
input wire [ 11:0 ] addr_h,
input wire [ 11:0 ] addr_v,
output reg [ 15:0 ] rgb_data
);
localparam black = 16'd0;
parameter height = 48; // 图片高度
parameter width = 48; // 图片宽度
reg [ 13:0 ] rom_address ; // ROM地址
wire [ 15:0 ] rom_data ; // 图片数据
wire flag_enable_out2 ; // 图片有效区域
wire flag_clear_rom_address ; // 地址清零
wire flag_begin_h ; // 图片显示行
wire flag_begin_v ; // 图片显示列
always @( posedge vga_clk or negedge rst_n) begin
if(!rst_n)begin
rgb_data = black;
end
else if ( flag_enable_out2 ) begin
rgb_data = rom_data;
end
else begin
rgb_data = black;
end
end
//ROM地址计数器
always @( posedge vga_clk or negedge rst_n ) begin
if ( !rst_n ) begin
rom_address <= 0;
end
else if ( flag_clear_rom_address ) begin //计数满清零
rom_address <= 0;
end
else if ( flag_enable_out2 ) begin //在有效区域内+1
rom_address <= rom_address + 1;
end
else begin //无效区域保持
rom_address <= rom_address;
end
end
assign flag_clear_rom_address = rom_address == height * width - 1;
assign flag_begin_h = addr_h > ( ( 640 - width ) / 2 ) && addr_h < ( ( 640 - width ) / 2 ) + width + 1;
assign flag_begin_v = addr_v > ( ( 480 - height )/2 ) && addr_v <( ( 480 - height )/2 ) + height + 1;
assign flag_enable_out2 = flag_begin_h && flag_begin_v;
//实例化ROM
rom rom_inst (
.address ( rom_address ),
.clock ( vga_clk ),
.q ( rom_data )
);
endmodule
vga驱动程序
module vga_display_pic (
input wire clk, //系统时钟
input wire rst_n, //复位
input wire [ 15:0 ] rgb_data, //16位RGB对应值
output wire vga_clk, //vga时钟 25M
output reg h_sync, //行同步信号
output reg v_sync, //场同步信号
output reg [ 11:0 ] addr_h, //行地址
output reg [ 11:0 ] addr_v, //列地址
output wire [ 4:0 ] rgb_r, //红基色
output wire [ 5:0 ] rgb_g, //绿基色
output wire [ 4:0 ] rgb_b //蓝基色
);
// 640 * 480 60HZ
localparam H_FRONT = 16; // 行同步前沿信号周期长
localparam H_SYNC = 96; // 行同步信号周期长
localparam H_BLACK = 48; // 行同步后沿信号周期长
localparam H_ACT = 640; // 行显示周期长
localparam V_FRONT = 11; // 场同步前沿信号周期长
localparam V_SYNC = 2; // 场同步信号周期长
localparam V_BLACK = 31; // 场同步后沿信号周期长
localparam V_ACT = 480; // 场显示周期长
localparam H_TOTAL = H_FRONT + H_SYNC + H_BLACK + H_ACT; // 行周期
localparam V_TOTAL = V_FRONT + V_SYNC + V_BLACK + V_ACT; // 列周期
reg [ 11:0 ] cnt_h ; // 行计数器
reg [ 11:0 ] cnt_v ; // 场计数器
reg [ 15:0 ] rgb ; // 对应显示颜色值
// 对应计数器开始、结束、计数信号
wire flag_enable_cnt_h ;
wire flag_clear_cnt_h ;
wire flag_enable_cnt_v ;
wire flag_clear_cnt_v ;
wire flag_add_cnt_v ;
wire valid_area ;
// 25M时钟
wire clk_25 ;
// 50M时钟
wire clk_50 ;
wire locked ;
//PLL
pll pll_inst (
.areset ( ~rst_n ),
.inclk0 ( clk ),
.c0 ( clk_50 ), //50M
.c1 ( clk_25 ), //25M
.locked (locked )
);
//根据不同分配率选择不同频率时钟
assign vga_clk = clk_25;
// 行计数
always @( posedge vga_clk or negedge rst_n ) begin
if ( !rst_n ) begin
cnt_h <= 0;
end
else if ( flag_enable_cnt_h ) begin
if ( flag_clear_cnt_h ) begin
cnt_h <= 0;
end
else begin
cnt_h <= cnt_h + 1;
end
end
else begin
cnt_h <= 0;
end
end
assign flag_enable_cnt_h = 1;
assign flag_clear_cnt_h = cnt_h == H_TOTAL - 1;
// 行同步信号
always @( posedge vga_clk or negedge rst_n ) begin
if ( !rst_n ) begin
h_sync <= 0;
end
else if ( cnt_h == H_SYNC - 1 ) begin // 同步周期时为1
h_sync <= 1;
end
else if ( flag_clear_cnt_h ) begin // 其余为0
h_sync <= 0;
end
else begin
h_sync <= h_sync;
end
end
// 场计数
always @( posedge vga_clk or negedge rst_n ) begin
if ( !rst_n ) begin
cnt_v <= 0;
end
else if ( flag_enable_cnt_v ) begin
if ( flag_clear_cnt_v ) begin
cnt_v <= 0;
end
else if ( flag_add_cnt_v ) begin
cnt_v <= cnt_v + 1;
end
else begin
cnt_v <= cnt_v;
end
end
else begin
cnt_v <= 0;
end
end
assign flag_enable_cnt_v = flag_enable_cnt_h;
assign flag_clear_cnt_v = cnt_v == V_TOTAL - 1;
assign flag_add_cnt_v = flag_clear_cnt_h;
// 场同步信号
always @( posedge vga_clk or negedge rst_n ) begin
if ( !rst_n ) begin
v_sync <= 0;
end
else if ( cnt_v == V_SYNC - 1 ) begin
v_sync <= 1;
end
else if ( flag_clear_cnt_v ) begin
v_sync <= 0;
end
else begin
v_sync <= v_sync;
end
end
// 对应有效区域行地址 1-640
always @( posedge vga_clk or negedge rst_n ) begin
if ( !rst_n ) begin
addr_h <= 0;
end
else if ( valid_area ) begin
addr_h <= cnt_h - H_SYNC - H_BLACK + 1;
end
else begin
addr_h <= 0;
end
end
// 对应有效区域列地址 1-480
always @( posedge vga_clk or negedge rst_n ) begin
if ( !rst_n ) begin
addr_v <= 0;
end
else if ( valid_area ) begin
addr_v <= cnt_v -V_SYNC - V_BLACK + 1;
end
else begin
addr_v <= 0;
end
end
// 有效显示区域
assign valid_area = cnt_h >= H_SYNC + H_BLACK && cnt_h <= H_SYNC + H_BLACK + H_ACT && cnt_v >= V_SYNC + V_BLACK && cnt_v <= V_SYNC + V_BLACK + V_ACT;
// 显示颜色
always @( posedge vga_clk or negedge rst_n ) begin
if ( !rst_n ) begin
rgb <= 16'h0;
end
else if ( valid_area ) begin
rgb <= rgb_data;
end
else begin
rgb <= 16'b0;
end
end
assign rgb_r = rgb[ 15:11 ];
assign rgb_g = rgb[ 10:5 ];
assign rgb_b = rgb[ 4:0 ];
endmodule
顶层模块
module vga_top (
input wire clk,
input wire rst_n,
output wire vga_clk,
output wire h_sync,
output wire v_sync,
output wire [ 4:0 ] rgb_r,
output wire [ 5:0 ] rgb_g,
output wire [ 4:0 ] rgb_b
);
wire [ 11:0 ] addr_h ;
wire [ 11:0 ] addr_v ;
wire [ 15:0 ] rgb_data ;
//模块例化
vga_display_pic (
.clk (clk ),
.rst_n (rst_n ),
.rgb_data (rgb_data ),
.vga_clk (vga_clk ),
.h_sync (h_sync ),
.v_sync (v_sync ),
.addr_h (addr_h ),
.addr_v (addr_v ),
.rgb_r (rgb_r ),
.rgb_g (rgb_g ),
.rgb_b (rgb_b )
);
//数据模块
data_drive u_data_drive(
.vga_clk ( vga_clk ),
.rst_n ( rst_n ),
.addr_h ( addr_h ),
.addr_v ( addr_v ),
.rgb_data ( rgb_data )
);
endmodule
显示效果:
总结
本次实验中我学会了VGA的显示原理不仅要逐行打印数据,而且还要将我们设定显示范围之外的数据显示为黑色,实验中我学会了很多Quantus的调试方法,也和同学们交流了经验,互帮互助,相互学习,最后大家都取得了很好的实验结果,多年后想起VGA我还是会想到我可爱的同学们。
参考
https://zhuanlan.zhihu.com/p/36440703
https://blog.csdn.net/qq_45659777/article/details/124834294?spm=1001.2014.3001.5502