代码:
module count(count,clk,rst);//?????11.
input clk,rst;
output [3:0] count;
reg [3:0] count;
always @(posedge clk)
if(rst) count<=4'b0;
else
if(count==4'b1010)
count<=4'b0;
else count<=count+1;
endmodule
测试:
module count_tb;
reg clk,rst;
wire [3:0]count;
count U1(
.count(count),
.clk(clk),
.rst(rst));
always #10 clk=~clk;
initial
begin
clk=1'b0;rst=1;
#20 rst=0;
#200 rst=1;
#200 $finish;
end
endmodule