HDLBits从零开始——第31题到第40题答案

目录

第31题：If statement

第32题：If statement latches

第33题：Case statement

第34题：Priority encoder

第35题：Priority encoder with casez

第36题：Avoiding latches

第37题：Conditional ternary operator

第38题：Reduction operators

第39题：Reduction: Even wider gates

第40题：Combinational for-loop:Vector reversal 2

---

第31题：If statement

module top_module
(
    input       a           ,  
    input       b           ,
    input       sel_b1      ,
    input       sel_b2      ,
    output wire out_assign  ,
    output reg  out_always   
); 

assign  out_assign = (sel_b1&sel_b2) ? b : a;

always@(*)
    if(sel_b1&sel_b2)
        out_always = b;
    else
        out_always = a;

endmodule

第32题：If statement latches

module top_module 
(
    input      cpu_overheated   ,
    output reg shut_off_computer,
    input      arrived          ,
    input      gas_tank_empty   ,
    output reg keep_driving  
);

    always@(*)
        if (cpu_overheated)
            shut_off_computer = 1;
        else
            shut_off_computer = 0;

    always@(*)
        if (~arrived)
            keep_driving = ~gas_tank_empty;
        else
            keep_driving = 0;


endmodule

第33题：Case statement

module top_module 
( 
    input       [2:0] sel   , 
    input       [3:0] data0 ,
    input       [3:0] data1 ,
    input       [3:0] data2 ,
    input       [3:0] data3 ,
    input       [3:0] data4 ,
    input       [3:0] data5 ,
    output reg  [3:0] out   
);

    always@(*)
        case(sel)
            3'd0:   out = data0;
            3'd1:   out = data1;
            3'd2:   out = data2;
            3'd3:   out = data3;
            3'd4:   out = data4;
            3'd5:   out = data5;
            default:    out = 4'b0;
        endcase

endmodule

第34题：Priority encoder

module top_module 
(
    input       [3:0] in    ,
    output reg  [1:0] pos  
);

always@(*)
    casex(in)
        4'b0001: pos = 2'd0;
        4'b0011: pos = 2'd0;
        4'b0101: pos = 2'd0;
        4'b0111: pos = 2'd0;
        4'b1001: pos = 2'd0;
        4'b1011: pos = 2'd0;
        4'b1101: pos = 2'd0;
        4'b1111: pos = 2'd0;
        4'b0010: pos = 2'd1;
        4'b0110: pos = 2'd1;
        4'b1010: pos = 2'd1;
        4'b1110: pos = 2'd1;
        4'b0100: pos = 2'd2;
        4'b1100: pos = 2'd2;
        4'b1000: pos = 2'd3;
        default: pos = 2'd0;
    endcase

endmodule

第35题：Priority encoder with casez

module top_module 
(
    input       [7:0] in    ,
    output reg  [2:0] pos  
);

always@(*)
    casez(in)
        8'bzzzzzzz1: pos = 3'd0;
        8'bzzzzzz10: pos = 3'd1;
        8'bzzzzz100: pos = 3'd2;
        8'bzzzz1000: pos = 3'd3;
        8'bzzz10000: pos = 3'd4;
        8'bzz100000: pos = 3'd5;
        8'bz1000000: pos = 3'd6;
        8'b10000000: pos = 3'd7;
        default: pos = 3'd0;
    endcase

endmodule

第36题：Avoiding latches

module top_module 
(
    input       [15:0]  scancode,
    output reg          left    ,
    output reg          down    ,
    output reg          right   ,
    output reg          up  
); 

always@(*)
    begin
        left = 1'b0;
        down = 1'b0;
        right= 1'b0;
        up   = 1'b0;
        case(scancode)
            16'he06b :  left = 1'b1;
            16'he072 :  down = 1'b1;
            16'he074 :  right= 1'b1;
            16'he075 :  up   = 1'b1;
            default:    ;
        endcase
    end

endmodule

第37题：Conditional ternary operator

module top_module 
(
    input  [7:0] a, b, c, d,
    output [7:0] min
);
    /*-----方案1-----*/
    //assign  min = (((((a>b) ? b : a) > c) ? c : ((a>b) ? b : a)) > d) ? d : ((((a>b) ? b : a) > c) ? c : ((a>b) ? b : a));

    /*-----方案2-----*/
    reg [7:0] min1;
    reg [7:0] min2;
    
    assign  min1 = (a>b) ? b : a;
    assign  min2 = (min1>c) ? c : min1;
    assign  min  = (min2>d) ? d : min2;
    
endmodule

第38题：Reduction operators

module top_module 
(
    input   [7:0]   in      ,
    output          parity
); 

assign  parity = ^in;

endmodule

第39题：Reduction: Even wider gates

module top_module
( 
    input   [99:0]  in      ,
    output          out_and ,
    output          out_or  ,
    output          out_xor 
);

assign  out_and = ∈
assign  out_or  = |in;
assign  out_xor = ^in;

endmodule

第40题：Combinational for-loop:Vector reversal 2

module top_module
( 
    input       [99:0] in ,
    output reg  [99:0] out
);

reg [6:0]   i;

always@(*)
    begin
        for(i = 0;i < 100;i = i + 1)
            out[i] = in[99 - i]; 
    end

endmodule