HDLBits从零开始——第21题到第30题答案

目录

第21题：Connecting ports by position

第22题：Connecting ports by name

第23题：Three modules

第24题：Modules and vectors

第25题：Adder 1

第26题：Adder 2

第27题：Carry-select adder

第28题：Adder-subtractor

第29题：Always blocks(combinational)

第30题：Always blocks(clocked)

---

第21题：Connecting ports by position

module top_module 
( 
    input   a   , 
    input   b   , 
    input   c   ,
    input   d   ,
    
    output  out1,
    output  out2
);

mod_a mod_a_inst( out1,out2,a,b,c,d );  

endmodule

第22题：Connecting ports by name

module top_module 
( 
    input   a       , 
    input   b       , 
    input   c       ,
    input   d       ,
    output  out1    ,
    output  out2
);

mod_a mod_a_inst
(
    .out1(out1), 
    .out2(out2), 

    .in1 (a), 
    .in2 (b), 
    .in3 (c), 
    .in4 (d)
);

endmodule

第23题：Three modules

module top_module 
( 
    input   clk , 
    input   d   , 
    output  q 
);

wire    q_out1;
wire    q_out2;

my_dff my_dff_inst1
(   
    .clk (clk), 
    .d   (d), 
    .q   (q_out1)
);

my_dff my_dff_inst2
(   
    .clk (clk), 
    .d   (q_out1), 
    .q   (q_out2)
);

my_dff my_dff_inst3
(   
    .clk (clk), 
    .d   (q_out2), 
    .q   (q)
);

endmodule

第24题：Modules and vectors

module top_module 
( 
    input        clk, 
    input  [7:0] d  , 
    input  [1:0] sel, 
    output [7:0] q 
);

wire    [7:0]   q_out1;
wire    [7:0]   q_out2;
wire    [7:0]   q_out3;

always@(*)
    case(sel)
        2'd0:  q = d;
        2'd1:  q = q_out1;
        2'd2:  q = q_out2;
        2'd3:  q = q_out3;
    endcase

my_dff8 my_dff8_inst1
( 
    .clk(clk), 
    .d  (d), 
    .q  (q_out1)
);

my_dff8 my_dff8_inst2
( 
    .clk(clk), 
    .d  (q_out1), 
    .q  (q_out2)
);

my_dff8 my_dff8_inst3
( 
    .clk(clk), 
    .d  (q_out2), 
    .q  (q_out3)
);

endmodule

第25题：Adder 1

module top_module
(
    input  [31:0] a   ,
    input  [31:0] b   ,
    output [31:0] sum
);

wire            cout    ;
wire    [15:0]  sum_out1;
wire    [15:0]  sum_out2;

assign  sum = {sum_out2,sum_out1};

add16 add16_inst1
( 
    .a   (a[15:0]), 
    .b   (b[15:0]), 
    .cin (1'b0), 
    .sum (sum_out1), 
    .cout(cout) 
);

add16 add16_inst2
( 
    .a   (a[31:16]), 
    .b   (b[31:16]), 
    .cin (cout), 
    .sum (sum_out2), 
    .cout() 
);

endmodule

第26题：Adder 2

module top_module 
(
    input   [31:0] a    ,
    input   [31:0] b    ,
    output  [31:0] sum
);

wire            cout    ;
wire    [15:0]  sum_out1;
wire    [15:0]  sum_out2;

assign  sum = {sum_out2,sum_out1};

add16 add16_inst1
( 
    .a   (a[15:0]), 
    .b   (b[15:0]), 
    .cin (1'b0), 
    .sum (sum_out1), 
    .cout(cout) 
);

add16 add16_inst2
( 
    .a   (a[31:16]), 
    .b   (b[31:16]), 
    .cin (cout), 
    .sum (sum_out2), 
    .cout() 
);

endmodule

module add1 
( 
    input a, 
    input b, 
    input cin,   
    
    output sum, 
    output cout 
);

    assign  sum = a ^ b ^ cin;
    assign  cout = (a & b) + ((a ^ b) & cin); 

endmodule

第27题：Carry-select adder

module top_module
(
    input  [31:0] a     ,
    input  [31:0] b     ,
    output [31:0] sum
);

wire    [15:0]  sum_out1;
wire    [15:0]  sum_out2;
wire    [15:0]  sum_out3;
wire            cout    ;
wire    [15:0]  high_out;

assign  high_out = cout ? sum_out3 : sum_out2;
assign  sum = {high_out,sum_out1};

add16 add16_inst1
( 
    .a   (a[15:0]), 
    .b   (b[15:0]), 
    .cin (1'b0), 
    .sum (sum_out1), 
    .cout(cout) 
);

add16 add16_inst2
( 
    .a   (a[31:16]), 
    .b   (b[31:16]), 
    .cin (1'b0), 
    .sum (sum_out2), 
    .cout() 
);

add16 add16_inst3
( 
    .a   (a[31:16]), 
    .b   (b[31:16]), 
    .cin (1'b1), 
    .sum (sum_out3), 
    .cout() 
);

endmodule

第28题：Adder-subtractor

module top_module
(
    input  [31:0] a     ,
    input  [31:0] b     ,
    input         sub   ,
    output [31:0] sum
);

wire    [31:0]  xor_out ;
wire    [15:0]  sum_out1;
wire    [15:0]  sum_out2;
wire            cout    ;

assign  xor_out = b^{32{sub}};
assign  sum = {sum_out2,sum_out1};

add16 add16_inst1
( 
    .a   (a[15:0]), 
    .b   (xor_out[15:0]), 
    .cin (sub), 
    .sum (sum_out1), 
    .cout(cout) 
);

add16 add16_inst2
( 
    .a   (a[31:16]), 
    .b   (xor_out[31:16]), 
    .cin (cout), 
    .sum (sum_out2), 
    .cout() 
);

endmodule

第29题：Always blocks(combinational)

module top_module
(
    input           a               , 
    input           b               ,
    output wire     out_assign      ,
    output reg      out_alwaysblock
);

assign  out_assign = a&b;

always@(*)
    out_alwaysblock = a&b;

endmodule

第30题：Always blocks(clocked)

module top_module
(
    input       clk             ,
    input       a               ,
    input       b               ,
    output wire out_assign      ,
    output reg  out_always_comb ,
    output reg  out_always_ff   
);

assign  out_assign = a^b;

always@(*)
    out_always_comb = a^b;
    
always@(posedge clk)
    out_always_ff <= a^b;

endmodule